Integrated circuit layout methods and layout structures

Details Integrated circuit layout methods and layout structures Integrated circuit layout methods and layout structures

1997-10-22

1999-10-12

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257355, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

059659254

ABSTRACT:
Disclosed is a semiconductor layout design for use in integrated circuits that use balance circuitry. The semiconductor layout design includes a set of four substantially self enclosing gate transistors being arranged symmetrically about a common point. Wherein, each of the set of four substantially self enclosing gate transistors have a gate width that is defined by a perimeter around each of the set of four substantially self enclosing gate transistors. The semiconductor layout design preferably includes a balanced circuit having a set of first transistors and a set of second transistors. The set of first transistors being wired diagonally across the set of four substantially self enclosing gate transistors. In a preferred embodiment, the set of second transistors are wired diagonally across the set of four substantially self enclosing gate transistors in a manner that ensures that the set of second transistors are wired substantially perpendicular to the set of first transistors.

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