Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-10-06
2002-07-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06421819
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an integrated circuit layout designing system and a power source eliminating method to be employed in the same. More particularly, the invention relates to a layout designing method of a Large Scale Integrated Circuit (LSI) having a basic power source wiring structure consisted of a power source wiring and a grounding wiring.
2. Description of the Related Art
Conventionally, an LSI layout designing system to be employed in a layout designing method of the type set forth above shown in
FIG. 10
is constructed with a function block (FB) library
1
, a function block library reading portion
2
, a power source and clock (CLK) wiring portion
3
, a function block arranging portion
4
, a wiring portion
6
, a wiring verifying portion
7
, a floor plan modifying portion
8
, a layout information outputting portion
9
, a function eliminating or chip size modifying portion
10
and a control memory
14
.
In the LSI layout designing system
13
constructed as set forth above, process operation shown in
FIG. 11
is performed by executing programs stored in the control memory
14
at respective portion upon performing layout design of the LSI.
Namely, when the function block library reading portion
2
reads out information necessary for layout design from the function block library
1
(step S
21
of FIG.
11
), the power source and clock wiring portion
3
performs power source wiring operation and clock wiring operation on the basis of the read out information. (step S
22
of FIG.
11
).
After the power source wiring operation and the clock wiring operation, the function block arranging portion
4
arranges the function blocks (step S
23
of
FIG. 11
) and the wiring portion
6
performs wiring operation for the arranged function blocks (step S
24
of FIG.
11
).
After completion of wiring operation by the wiring portion
6
, the wiring verifying portion
7
checks whether not yet formed wiring is present or not (step S
25
of FIG.
11
). The wiring verifying portion
7
makes judgment whether not yet formed wiring is present and integration is possible. If the result of judgment is positive, the floor plan modifying portion
8
modifies a floor plan and returns control to the function block library reading portion
2
(step S
27
of FIG.
11
).
If the result of checking in the wiring verifying portion
7
shows that the not yet formed wiring is not present, the lay out information outputting portion
9
outputs the layout information generated through the foregoing process (step S
26
of FIG.
11
). On the other hand, if the result of judgment in the floor plan modifying portion
8
shows that not yet formed wiring is present but no further integration is possible, the function eliminating or chip size modifying portion
10
eliminates the function or modifies a chip size and then returns control to the function block library reading portion
2
(step S
28
of FIG.
11
).
In the conventional LSI layout designing method set forth above, if a space is not enough for providing signal wiring, a region where not yet formed wiring is present, is processed for forming the requiring wiring by-passing the existing wiring by automatic correction or manual area correction. Therefore, delay period can become longer for extra length of wiring bypassing the existing signal wiring. This can be a cause of restriction of speeding up of LSI.
On the other hand, if channel wiring region for the signal is too small to form all of required wiring, it becomes inherent to modify layout or floor plan, to modify logic, to eliminate logical function or so forth. This causes significant increase of process steps for repeated design due to floor plan modification or so forth.
SUMMARY OF THE INVENTION
The present invention has been worked out in view of the problem set forth above. Therefore, it is an object of the present invention to provide an integrated circuit layout design system and a power source eliminating method to be employed in the same, which can realize high wiring receiving capability, can achieve speeding up by shortening delay period of signal wiring, significantly eliminate design load, and can prevent lowering of function.
According to the first aspect of the present invention, an integrated circuit layout designing system for performing a layout design of an integrated circuit having a basic power source wiring structure consisted of a power source wiring and a grounding wiring, comprises:
eliminating means for eliminating the power source wiring and a power source via other than the basic power source wiring structure for supplying a power to a function block after arranging the function block on the basic power source wiring structure.
According to the second aspect of the present invention, a power source eliminating method in a layout design of an integrated circuit having a basic power source wiring structure consisted of a power source wiring and a grounding wiring, comprises a step of:
eliminating the power source wiring and a power source via other than the basic power source wiring structure for supplying a power to a function block after arranging the function block on the basic power source wiring structure.
According to the third aspect of the present invention, a storage medium recording a power source elimination control program to be executed by a computer for eliminating a power source wiring in a layout design of an integrated circuit having a basic power source wiring structure consisted of a power source wiring and a grounding wiring, the power source elimination control program comprises a step of:
eliminating the power source wiring and a power source via other than the basic power source wiring structure for supplying a power to a function block after arranging the function block on the basic power source wiring structure.
Namely, the power source eliminating method in the integrated circuit layout according to the present invention maintains the basic power source wiring for supplying sufficient power to the function block after arranging the function and eliminates remaining power source wiring and the power source via, by making the layout designing tool to recognize the power source wiring structure.
By this, since the channel wiring region for the signal can be certainly obtained in the region where the power source is eliminated, higher package density of the LSI can be achieved and by-pass wiring can be reduced to contribute for speeding up of the LSI.
REFERENCES:
patent: 5347465 (1994-09-01), Ferreri et al.
patent: 6230403 (2001-05-01), Skoolicas
patent: 6-29502 (1994-02-01), None
patent: 6-244387 (1994-09-01), None
patent: 9-36238 (1997-02-01), None
patent: 10-209285 (1998-08-01), None
patent: 11-145293 (1999-05-01), None
Do Thuan
Smith Matthew
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