Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-03
2007-07-03
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S110000, C382S149000, C382S154000, C714S025000
Reexamination Certificate
active
10906553
ABSTRACT:
Method, system and program product for determining a critical area in a region of an integrated circuit layout using Voronoi diagrams and shape biasing. The method includes the steps of generating a biased Voronoi diagram based on a layout geometry of the region and incorporating a shape bias; and determining the critical area for the region using the biased Voronoi diagram.
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Allen Robert J.
Chan Peter K.
Papadopoulou Evanthia
Prue Sarah C.
Tan Mervyn Y.
Hoffman Warnick & D'Alessandro LLC
International Business Machines - Corporation
Kik Phallaka
Kotulak Richard M.
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