Integrated-circuit isolation structure and method for...

Details Integrated-circuit isolation structure and method for... Integrated-circuit isolation structure and method for...

1999-05-13

2002-04-02

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S396000

Reexamination Certificate

active

06365946

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to integrated circuits (ICs), and more particularly to an improved isolation structure and a method for forming the same. For example, the isolation structure reduces “hump” effects in transistors that are adjacent to the structure, particularly in transistors having a feature size of 0.25 microns (&mgr;m) or less.
BACKGROUND OF THE INVENTION
To meet the industry demand for ICs that pack greater functionality into the same or a smaller die area, IC manufacturers continue to research and develop processes that allow integrated devices such as transistors to have smaller geometries. For example, a few years ago, many IC manufacturers used a 4 &mgr;m process, which can form devices having a feature size (e.g., the width of a transistor gate) as small as 4 &mgr;m. But today, 1 &mgr;m processes are common, and 0.25 &mgr;m, 0.18 &mgr;m and 0.1 &mgr;m processes are under development. These smaller-geometry processes allow the formation of integrated devices having smaller geometries. Consequently, such processes allow more devices—and thus more functionality—on a given die area than larger-geometry processes do.
Unfortunately, merely scaling down the dimensions of an integrated device to take advantage of a smaller-geometry process may render the device inoperable. For example, due to known short-channel effects, a transistor having a gate width of 4 &mgr;m may operate improperly if it is scaled down to have a gate width of 1 &mgr;m.
FIG. 1
is a cross-sectional view of a conventional silicon-trench isolation (STI) structure
10
, which is part of an IC
11
such as a memory circuit. The IC
11
includes transistors
12
a
and
12
b
, which are disposed in a substrate
13
having a surface
14
and corners
16
a
and
16
b
. The transistors
12
a
and
12
b
include respective body regions
18
a
and
18
b
, which are disposed in the substrate
13
and which electrically invert during transistor operation to form respective channel regions. Gate insulators
20
a
and
20
b
are respectively disposed on the body regions
16
a
and
16
b
. A conductor
22
, such as a word line, extends over the isolation structure
10
and the gate insulators
20
a
and
20
b
and acts as a gate electrode for both the transistors
12
a
and
12
b.
Unfortunately, the isolation structure
10
may cause the transistors
12
a
and
12
b
to operate improperly. The isolation structure
10
includes an isolation trench
24
disposed in the substrate
13
. The trench
24
is filled with an insulator
26
having side walls that often taper inwardly as they extend from the trench
24
above the surface
14
of the substrate
13
. This narrowing forms gaps
28
a
and
28
b
, which allow the gate conductor
20
to closely overlap the corners
16
a
and
16
b
, respectively. During operation of the transistors
12
a
and
12
b
, this overlap often causes undesirable fringe, i.e., “hump,” effects in the respective regions of the transistors' electric fields near the corners
16
a
and
16
b
. If the transistors
12
a
and
12
b
have relatively large feature sizes, then these hump effects typically have only a negligible affect on transistor operation. But if the transistors
12
a
and
12
b
have relatively small feature sizes, particularly feature sizes of 0.25 &mgr;m or less, then these hump effects may severely degrade the transistor operation, and may even render the transistors
12
a
and
12
b
unusable. Furthermore, even if the side walls of the insulator
26
are straight outside of the trench
24
, the conductor
22
may still be close enough to the corners
16
a
and
16
b
to cause significant hump effects.
SUMMARY OF THE INVENTION
In one aspect of the invention, an IC isolation structure includes a recess disposed in a conductive layer having a surface portion. The recess has a side wall adjacent to the surface portion, and the isolation structure also includes an insulator disposed in the recess and overlapping the surface portion.
Thus, if a transistor is disposed in the conductive layer adjacent to the recess side wall, the overlapping portion of the insulator increases the distance between the recess corner and the gate electrode. This increased distance reduces hump effects to tolerable levels.


REFERENCES:
patent: 4578128 (1986-03-01), Mundt et al.
patent: 5306940 (1994-04-01), Yamazaki
patent: 5362981 (1994-11-01), Sato et al.
patent: 5585659 (1996-12-01), Kobayashi et al.
patent: 5777370 (1998-07-01), Omid-Zohoor et al.
patent: 5969393 (1999-10-01), Noguchi
patent: 6005279 (1999-12-01), Luning
patent: 6114741 (2000-09-01), Joyner et al.

Affiliated with

Also associated with

Rating

Integrated-circuit isolation structure and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated-circuit isolation structure and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated-circuit isolation structure and method for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2845520