Integrated circuit isolation process

Details Integrated circuit isolation process Integrated circuit isolation process

1989-03-10

1990-01-09

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156648, 156653, 156657, 1566591, 156662, 437 67, B44C 122, H01L 21306, C03C 1500, C03C 2506

Patent

active

048926140

ABSTRACT:
A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). the recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.

REFERENCES:
patent: 4471525 (1984-09-01), Sasaki
patent: 4472240 (1984-09-01), Kameyama
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4580330 (1986-04-01), Pollack et al.
patent: 4671851 (1987-06-01), Beyer et al.
Magdo and Magdo, "Silicon Nitride Sidewall Recessed Oxide Isolation," IBM Technical Disclosure Bulletin, vol. 24, No. 9, (Feb. 1982), pp. 4741-4743.

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