Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
1999-09-23
2001-12-04
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
Reexamination Certificate
active
06326281
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to electronic semiconductor devices, and, more particularly, to integrated circuits with selectively grown silicon isolation structures and fabrication methods for such structures.
The advancement of the silicon microelectronic technology towards higher operating frequencies and higher packing densities leads to the application of more complex manufacturing technologies. Epitaxial growth is used to obtain sharper doping transitions between very thin layers as a replacement for ion implantation. For selective epitaxial growth (SEG) of silicon the Si epitaxial deposition is confined to openings in masking layers formed by oxidizing the Si surface or by chemical vapor deposition (CVD) of masking films like silicon nitride. Windows in the masking layer are defined by photolithography and etching.
The challenge in SEG is to develop processes for the mask formation, the Si surface preparation, and the epitaxial growth which maintain the advantages of doping control and eliminate deleterious effects caused by the mask sidewalls, such as defects near the sidewalls and faceted growth. J. O. Borland et al. (Solid State Technology, August 1985) reviewed dielectric isolation technologies and pointed out that SEG offers improvements for submicrometer CMOS devices. V. Silvestri et al. in U.S. Pat. Nos. 4,526,631 and 4,689,656 disclose how SEG, based on specific processes, can be applied to the formation of void-free isolation patterns by filling deep silicon trenches when the growth is confined to the bottom of the mask window. To achieve the required wafer flatness a thick SiO
2
layer had to be deposited and then planarized by chemical mechanical polishing (CMP). Liaw et al. in U.S. Pat. No. 4,786,615 disclose improved planarity of epitaxial surfaces obtained by growing two superimposed epitaxial layers at temperatures above and below a transition temperature, Tt, in this case, approximately 975° C. Above Tt, the growth rate is “mass transport limited”; i.e., the silicon source species has to diffuse through a boundary layer on the seed surface. The thickness of the boundary layer is influenced by the surface topology and by the gas flow and pressure conditions. Below Tt the growth rate is controlled by the reaction rate of surface processes which involve the movement of adsorbed silicon from the landing site to the place where the Si is incorporated into the crystal; e.g., at surface ledges and kinks. Below Tt, in the kinetically controlled regime, the growth rate depends strongly on the surface orientation of the seed and the growth of facets was observed. Flat surfaces were obtained by growing first at T<Tt, followed by growth at T>Tt. A thinner boundary layer at the mask edges caused a higher growth rate adding material in areas which earlier had a reduced thickness due to facet growth.
T. O. Sedgwick et al. (J.Electrochem.Soc. October 1991) showed that oxygen background reduction extends the Si epitaxial growth temperature to as low as 600° C. Under this growth condition the area next to the <
110
> oriented mask sidewall is heavily twinned and thicker than the remaining epitaxial layer. A. Ishitani et al. (Jap.J.Appl.Phys. May 1989) studied the development of <
311
> oriented facets, using a single layer growth mask. In <
100
> oriented square windows <
311
> facets developed only in the rounded mask corners. This mask sidewall orientation also led to stacking-fault-free silicon layers when grown at low temperature, in this system 950° C.
More recently, J. M. Sherman et al. (IEEE Elec. Device Letters, June 1996), report studies of selective Si growth and the achievement of a reduction, but not complete elimination, of growth mask sidewall effects.
Summarizing prior art of Si SEG, deleterious effects of the mask sidewalls on the epilayer morphology and on electrical characteristics were reduced, but not eliminated, by optimizing the wafer surface preparation and growth parameters such as temperature, pressure, gas composition (HCl concentration), and by restricting the mask sidewall alignment to the <
100
> orientation.
SUMMARY OF THE INVENTION
The present invention provides silicon isolation structures analogous to shallow trench isolation (STI) by epitaxial growth of silicon in openings in a silicon-nitride-on-silicon-oxide mask on a silicon substrate with an initial etch of the oxide to undercut the nitride yielding facet-free silicon epitaxy.
This has advantages including a nitride isolation surface to eliminate insulator loss during wet etching and surface preparation.
REFERENCES:
patent: 4111724 (1978-09-01), Ogiue et al.
patent: 4283837 (1981-08-01), Slob
Ashburn Stanton P.
Grider Douglas T.
Nandakumar Mahalingam
Violette Katherine E.
Wise Rick L.
Brady W. James
Elms Richard
Hoel Carlton H.
Owens Beth E.
Telecky , Jr. Frederick J.
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