Integrated circuit interconnect structure having reduced...

Details Integrated circuit interconnect structure having reduced... Integrated circuit interconnect structure having reduced...

2007-04-03

2007-04-03

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000

Reexamination Certificate

active

11152360

ABSTRACT:
An interconnect structure in which “diagonal” and “straight” interconnect lines are interleaved to minimize coupling between adjacent interconnect lines. An interconnect structure for an integrated circuit comprises rows and columns of tiles. Interconnect lines extend at least in part along a first column of the tiles, the interconnect lines including straight and diagonal interconnect lines. A “straight” interconnect line interconnects at least two tiles in the first column, and a “diagonal” interconnect line interconnects a tile in the first column with at least one tile in a different column and row. The interconnect lines are laid out in parallel fashion such that no straight interconnect line is physically adjacent to more than one other straight interconnect line, and no diagonal interconnect line is physically adjacent to more than one other diagonal interconnect line. Optionally, no two physically adjacent interconnect lines drive in the same direction within the first column.

REFERENCES:
patent: 5801546 (1998-09-01), Pierce et al.
patent: 5818730 (1998-10-01), Young
patent: 5828230 (1998-10-01), Young
patent: 5914616 (1999-06-01), Young et al.
patent: 5920202 (1999-07-01), Young et al.
patent: 5963050 (1999-10-01), Young et al.
patent: 6081914 (2000-06-01), Chaudhary
patent: 6163167 (2000-12-01), Young
patent: 6188091 (2001-02-01), Young
patent: 6204690 (2001-03-01), Young et al.
U.S. Appl. No. 11/151,796, filed Jun. 14, 2005, Young et al.
U.S. Appl. No. 11/151,819, filed Jun. 14, 2005, Young et al.
U.S. Appl. No. 11/151,892, filed Jun. 14, 2005, Young et al.
U.S. Appl. No. 11/151,915, filed Jun. 14, 2005, Young et al.
U.S. Appl. No. 11/151,938, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/151,939, filed Jun. 14, 2005, Chirania et al.
U.S. Appl. No. 11/151,986, filed Jun. 14, 2005, Simkins.
U.S. Appl. No. 11/151,987, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/151,988, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/152,010, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/152,012, filed Jun. 14, 2005, Pham et al.
U.S. Appl. No. 11/152,358, filed Jun. 14, 2005, Bauer et al.
U.S. Appl. No. 11/152,359, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/152,439, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/152,572, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/152,590, filed Jun. 14, 2005, Kondapalli et al.
U.S. Appl. No. 11/152,637, filed Jun. 14, 2005, Young.
U.S. Appl. No. 11/152,736, filed Jun. 14, 2005, Kondapalli et al.
U.S. Appl. No. 11/152,737, filed Jun. 14, 2005, Kondapalli et al.
U.S. Appl. No. 11/152,763, filed Jun. 14, 2005, Young.
Lucent Technologies; “Field Programmable Gate Arrays Data Book”; published Oct. 1996; pp. 2-9 through 2-28.
Altera Corporation; “Stratix Device Handbook; vol. 1”; “2. Stratix Architecture”; published Sep. 2004; pp. 2-1 through 2-20.
Xilinx, Inc.; “Virtex-II Platform FPGA Handbook”; published Dec. 2000; available from Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124, pp. 33-75.
Xilinx, Inc.; “Programmable Logic Data Book 2000”; Published Apr. 2000; available from Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124; pp. 3-75 through 3-96.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Oct. 14, 2002; available from Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124; pp. 19-71.
Altera Corporation; “FLEX 10K Embedded Programmable Logic Family Data Sheet”; Digital Library 1996; pp. 31-53, no month.
Xilinx, Inc.; “Programmable Logic Data Book 1996”; published Sep. 1996; available from Xilinx, Inc. 2100 Logic Drive, San Jose, California 95124; pp. 4-5 through 4-45, 4-181 through 4-196, 4-253 through 4-264, and 4-289 through 4-302.
Xilinx, Inc.; “The Programmable Logic Data Book 1994”; published 1994; available from Xilinx, Inc, 2100 Logic Drive, San Jose, California 95124; pp. 2-187 through 2-195, no month.
Altera Corporation; “Stratix-II Device Handbook”; vol. I; published Mar. 2005; pp. 2-1 through 2-28.
Steven Elzinga et al., “Design Tips for HDL Implementation of Architecture Functions”; XAPP 215 (v1.0); Jun. 28, 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-13.

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