Integrated circuit interconnect and method

Details Integrated circuit interconnect and method Integrated circuit interconnect and method

1999-12-21

2002-03-19

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

C438S700000, C438S723000, C438S724000

Reexamination Certificate

active

06358849

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to electronic semiconductor devices, and, more particularly, to dielectric structures and fabrication methods for such structures.
The performance of high density integrated circuits is dominated by metal interconnect level RC time delays due to the resistivity of the metal lines and the capacitive coupling between adjacent lines. The capacitive coupling can be reduced by decreasing the relative permittivity (dielectric constant, k) of the dielectric (electrical insulator) between adjacent lines.
Various dielectric materials have been suggested for use in silicon integrated circuits to replace the commonly used silicon dioxide (k about 4.0). The leading candidates are fluorinated silicon dioxide (k about 3.0-4.0), organic polymers such as polyimide, parylene, bis-benzocyclobutene (BCB), amorphous teflon (k about 1.9-3.9), and porous dielectrics such as silicon dioxide based xerogels (k dependent upon pore size and typically 1.3-3.0).
Similarly, decreasing the resistivity of the interconnect metal by substituting copper (or silver) for the commonly used aluminum and tungsten will also reduce the RC time constant.
Copper interconnects typically require a dual inlaid (dual damascene) process for fabrication which uses a first via etch through two dielectric layers followed by a second interconnect trench etch through just the top dielectric. Then the trench and via are filled with copper by blanket deposition plus planarization to remove copper outside of the trench and via; chemical mechanical polishing (CMP) provides the planarization. However, photoresist exposure and development for the trench etch has problems at the vias, and subsequent trench etch can breakthrough the interconnect passivation at the via bottoms.
Thus the current fabrication methods for copper interconnects using CMP processing have manufacturability problems.
SUMMARY OF THE INVENTION
The present invention provides a temporary filler for etched vias during dual inlaid interconnect trench processing.
This has the advantages of robust dual inlaid processing.


REFERENCES:
patent: 4888087 (1989-12-01), Moslehi et al.
patent: 5488013 (1996-01-01), Geffken et al.
patent: 5635423 (1997-06-01), Huang et al.

Affiliated with

Also associated with

Rating

Integrated circuit interconnect and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit interconnect and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit interconnect and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2838076