Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-22
2003-11-25
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S326000
Reexamination Certificate
active
06653684
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacturing of integrated circuits including various types of elementary components, and especially logic MOS transistors, of complementary types (CMOS), EPROM cells, and transistors having a higher breakdown voltage than logic MOS transistors. Of course the present invention does not exclude other components, and even bipolar components, from being formed in the same integrated circuit.
2. Discussion of the Related Art
FIGS. 1A
,
1
B, and
1
C show respectively a cross-section view along a line A—A, a top view, and a cross-section view along a line C—C of an EPROM cell.
FIGS. 2A
,
2
B, and
2
C show respectively a cross-section view along a line A—A, a top view, and a cross-section view along a line C—C of a logic MOS transistor. The two components are formed in the same integrated circuit. The case where the integrated circuit structure is extremely miniaturized is more specifically considered, for example, structures in which the width of an elementary pattern may be 0.25 &mgr;m.
The elementary components are formed in areas that may be specifically doped of a P-type substrate
1
. This substrate will generally be an epitaxial layer formed on a silicon substrate. But it may also be a thin silicon layer on an insulator. The various components are separated from one another by thick oxide areas
3
. Preferably, the thick oxide areas are made according to a so-called STI (shallow trench insulation) technique consisting of digging trenches into the substrate, then filling the trenches with oxide. This filling is generally performed by uniform deposition of an oxide layer followed by a chem-mech polishing. Although the upper surface of the oxide filling trenches
3
is shown as being exactly at the same level as the upper surface of silicon substrate
1
in the appended drawings, there may in practice exist a slight jutting out.
The EPROM cell includes a floating gate
5
formed of a portion of a first polysilicon layer formed above a thin oxide layer
7
, sometimes called a tunnel oxide. The floating gate is coated and surrounded with a thin insulator layer, for example an oxide-nitride-oxide (ONO) sandwich, and is then coated with a portion of a second polysilicon layer
11
forming a control gate and, in the embodiment shown, surrounded therewith. Spacers
13
are formed along the lateral walls of second polysilicon layer
11
. Various implantation steps are provided to form source and drain regions. A first implantation
15
-
1
,
15
-
2
is masked by first polysilicon layer
5
. A second implantation
16
-
1
,
16
-
2
is masked by second polysilicon layer
11
. A third implantation
17
-
1
,
17
-
2
of high doping level is masked by the structure widened by spacers
13
.
The active area of the EPROM cell corresponds in the top view of
FIG. 1B
to the inside of a rectangle
20
surrounded with thick oxide. The entire structure is coated with a thick insulating layer
23
, preferably planarized. In this insulating layer are formed openings
24
,
25
,
26
intended for respectively making contact with source
17
-
1
, drain
17
-
2
, and control gate
11
. As better shown in
FIGS. 1B and 1C
, the control gate preferably continues above thick oxide
3
at the locations of the contacting areas.
In the MOS transistor illustrated in
FIGS. 2A
,
2
B,
2
C, an active area is defined in a portion of the substrate. In the top view of
FIG. 2B
, the active area corresponds to the inside of a rectangle
30
outside of which exists thick oxide area
3
. It should be noted that this substrate portion is not necessarily of the same nature as the P substrate portion in which the EPROM cell is formed. It may be an area in which a P well has been formed by a specific diffusion. The MOS transistor includes a gate
111
separated from the substrate by a thin oxide
31
. At the periphery of gate
111
is formed a spacer
113
. The source and drain regions correspond to first implantations
116
-
1
,
116
-
2
delimited by gate
111
and to second implantations
117
-
1
,
117
-
2
delimited by spacers
113
. As previously, the structure is coated with a layer of a thick insulator
23
in which are formed source, drain, and gate contact openings
34
,
35
, and
36
. As in the preceding case, the gate contact preferably is displaced above a thick oxide region.
The representations of
FIGS. 1A-1C
and
2
A-
2
C are extremely simplified and are only intended for having the type of structure of the described components understood. The illustrated shapes do not correspond to real shapes. Especially, in the contacting areas, instead of forming a single contact opening, several parallel contact openings are generally formed to increase the contact surface area without increasing the surface area of each of the openings. On the other hand, the widths of the various layers are not to scale. As an example, a configuration having the following parameters will be considered:
length L of gate 111 of the MOS transistor
0.25
&mgr;m,
thickness of gate oxide 31 of the MOS transistor
5
nm,
thickness of tunnel oxide 7 of the EPROM cell
11
nm,
thickness of the polysilicon layer
100
nm,
thickness of ONO layer 9
16
nm,
thickness of polysilicon layer 11
250
nm,
total thickness of insulating layer 23
1
&mgr;m.
The order of the manufacturing steps of such a structure is for example the following:
1) forming the trenches filled with an insulator to define active areas;
2) implanting P and N wells, respectively for N-channel MOS transistors and P-channel MOS transistors;
3) first EPROM cell manufacturing steps, that is, depositing and etching tunnel oxide
7
and first polysilicon layer
5
and coating by an ONO layer
9
;
4) removing layers specific to the EPROM cells in the MOS transistor areas;
5) forming the gate oxides of the MOS transistors;
6) for the MOS transistors and the EPROM cells: forming a second polysilicon level and etching this level along the contour of the MOS transistor gates and of the EPROM cell control gates; forming spacers;
7) depositing a thick insulating layer
23
and forming openings in this thick insulating layer to contact the gate, control gate, source, and drain regions.
Of course, a real process includes many other steps that have not been mentioned herein, especially the various steps of implantation and diffusion to form the source and drain regions and to dope the various polysilicon layers.
As concerns the etching of the contact openings, source and drain openings
24
,
25
,
34
,
35
, contact openings on control gates of EEPROM cells
26
, and contact openings on gates of MOS transistors
36
are desired to be simultaneously formed. Given that openings
26
and
36
emerge into relatively thick polysilicon layers, there is no particular problem if the etching between oxide
23
and the polysilicon is not extremely selective since the polysilicon thickness is sufficient to absorb a slight overetching.
It should be noted that, in these structures, no contact is provided on polysilicon regions corresponding to the first floating gate polysilicon layer
5
, which is generally very thin, of a thickness on the order of 100 nm, to avoid step crossing problems for the following layers. Given the thinness of layer
5
, the forming of a contact opening would risk, in case of a poor etch selectivity between oxide
23
and the polysilicon, piercing polysilicon layer
5
and even, after this, the underlying oxide layers. Structures likely to exhibit significant defects would then be obtained.
In integrated circuits including these as previously described, MOS transistors of very small dimensions, having a gate length on the order of 0.25 &mgr;m or less, it has been seen that the thickness of the gate oxide is on the order of 5 nm. This means that such transistors cannot securely withstand voltages over 2.5 volts. Now, EPROM cells of the illustrated type, having for example a tunnel oxide thickness on the order of 11 nm, r
Fournel Richard
Mazaleyrat Eric
Morris James N.
STMicroelectronics S.A.
Wilson Allan R.
Wolf Greenfield & Sacks P.C.
LandOfFree
Integrated circuit including high-voltage and logic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit including high-voltage and logic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit including high-voltage and logic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3166530