Integrated circuit including built-in self test circuit to...

Static information storage and retrieval – Read/write circuit – Testing

Reexamination Certificate

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C714S733000

Reexamination Certificate

active

07876633

ABSTRACT:
An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array.

REFERENCES:
patent: 6728910 (2004-04-01), Huang
patent: 7222272 (2007-05-01), Takazawa et al.
patent: 7426663 (2008-09-01), Takazawa et al.
patent: 7729185 (2010-06-01), Shirur et al.
patent: 2003/0222283 (2003-12-01), Takazawa et al.
patent: 2007/0198880 (2007-08-01), Takazawa et al.
patent: 2009/0063917 (2009-03-01), Tokunaga et al.
patent: 2002-32999 (2002-01-01), None
patent: 2003-346500 (2003-12-01), None

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