Integrated circuit identification

Details Integrated circuit identification Integrated circuit identification

2007-05-22

2007-05-22

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C355S067000, C257SE21521, C257SE21522

Reexamination Certificate

active

10942608

ABSTRACT:
A method for marking a semiconductor wafer302includes the steps of: providing a reticle300including liquid crystal pixels; positioning the semiconductor wafer in proximity to the reticle; directing radiation through a first plurality of the pixels onto a first location on the wafer; changing the relative positions of the semiconductor wafer and the reticle; and directing radiation through a second plurality of the pixels onto a second location on the wafer. The first plurality of pixels can be used to form a first mark and the second plurality of pixels can be used to form a second mark, wherein the second mark is different from the first mark. The marks can be made of a pattern of dots in order to save space. The pixels can be selected to form certain marks by using a computer304to turn on or off a transistor that may be associated with each pixel. Also described is a system for marking a semiconductor wafer. The system includes a wafer mount301; a radiation source306in proximity to the wafer mount; a reticle300which includes liquid crystal pixels and that is positionable between the radiation source and the wafer mount; and a mechanism303for changing the relative positions of the reticle and the wafer mount. The radiation source can be non-coherent far-ultraviolet, near-ultraviolet, or visible sources, or a laser.

REFERENCES:
patent: 5525808 (1996-06-01), Irie et al.
patent: 6312134 (2001-11-01), Jain et al.
patent: 6482199 (2002-11-01), Neev
“Nonlaminate Micro Stereolithography Using TFT LCD” T. Hayashi et al. 1stEuspen Topical Conference on Fabrication and Metrology in Nanotechnology and 2ndGeneral Meeting of the European Society for Precision Engineering and Nanotechnology, May 28-30, 2000, pp. 98-106.
Study on Nonlaminate Micro Stereolithography Using LCD Mask (1streport)—Nonlaminate Fabrication Using Gray Scale Image, T. Hayashi et al. Journal of the Japan Society for Precision Engineering. vol. 67, No. 4, pp. 628-632, 2001.

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