Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-15
2009-06-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07552412
ABSTRACT:
A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeffas an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeffby less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.
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Abbaspour Soroush
Ditlow Gary S.
Kashyap Chandramouli V.
Puri Ruchir
International Business Machines - Corporation
Law Office of Charles W. Peterson, Jr.
Siek Vuthe
Verminski, Esq. Brian P.
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