Integrated circuit (IC) chip design method, program product...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

active

07552412

ABSTRACT:
A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeffas an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeffby less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

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Agarwal et al. “An Effective Capacitive Based Driver Output Model for On-Chip RLC Interconnects,” ACM, Jun. 2-6, 2003, pp. 376-381.
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Mei et al., “An Accurate Low Iteration Algorithm for Effective Capacitance Computation,” ACM, Jul. 2004, pp. 1-6.
Kahng et al., “Improved Effective Capacitance Computations for Use in Logic and Layout Optimization,” IEEE, 1999, pp. 1-5.

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