Integrated circuit I/O node useable for configuration input at r

Details Integrated circuit I/O node useable for configuration input at r Integrated circuit I/O node useable for configuration input at r

1996-04-19

1998-07-07

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 37, H03K 19173

Patent

active

057774889

ABSTRACT:
The invention provides a method and system in which a single pin coupled to an integrated circuit (IC) chip is used to enter configuration information at a power-up time or a reset time (collectively referred to herein as a "reset time" or "reset interval"), and is also used to display output information during normal operation. The pin is coupled to a memory device, so as to store configuration information received during the reset interval. The pin is also coupled to an output driver controlled by a gate which combines output data with a signal indicating reset time, so as to put the output driver into a high impedance state during reset time when the input configuration data is being stored into the device and to drive the pin with the output value during non-reset times. Thus, a user of the IC may cause the memory to receive configuration information from the pin at power-up or during another reset time, while having the pin output normal data at times other than the reset interval.

REFERENCES:
patent: 5051622 (1991-09-01), Pleva
patent: 5175859 (1992-12-01), Miller et al.
patent: 5216714 (1993-06-01), Speiser
patent: 5323463 (1994-06-01), Speiser
patent: 5594362 (1997-01-01), Owen
patent: 5608341 (1997-03-01), Andersson

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