Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-11-24
2001-10-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S057000
Reexamination Certificate
active
06300800
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and, more particularly, to an input-output (I/O) buffer, which is capable of interfacing with voltages higher than its I/O voltage.
CMOS integrated circuits are typically provided with tri-state I/O buffers that are selectively operable between a low-impedance drive mode and a high-impedance, tri-state mode in which the buffers appear transparent to the output pad terminals with which they are connected. Advancements in semiconductor fabrication technology enable the geometries of semiconductor devices to be progressively reduced so that more devices can fit on a single integrated circuit. As a result, core voltages of integrated circuits are being reduced to prevent damage to the small devices and to reduce overall power consumption of the integrated circuit. For example, power supplies are now being reduced from 5V to 3.3V, from 3.3V to 2.5V, and from 2.5V to 1.8V.
However, low voltage CMOS devices are often interconnected at a board level to integrated circuits having older technology and operating at higher core voltages such as 3.3V or 5V. It is therefore desirable to provide an I/O buffer that is tolerant to pad voltages that are larger than the I/O voltage without exceeding the tolerance levels of the devices within the buffer and without drawing leakage current from the pad terminal while in the tri-state mode.
SUMMARY OF THE INVENTION
The integrated circuit output buffer of the present invention includes a core terminal, a pad terminal, a pad pull-up transistor, a pad pull-down transistor, a pull-up voltage protection transistor, and a selectively conductive pad voltage feedback path. The pad pull-up transistor and the pad pull-down transistor are coupled to the pad terminal and are biased to respectively charge and discharge the pad terminal in response to a data signal received on the core terminal. The pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal and a well terminal. The selectively conductive pad voltage feedback path is coupled between the pad terminal and the well terminal of the pull-up voltage protection transistor.
Another aspect of the present invention relates to a method of operating a tri-state buffer having a pad pull-down transistor, which is coupled to a pad terminal, and a pad pull-up transistor, which is coupled to the pad terminal through a pull-up voltage protection transistor. The method includes: operating the tri-state buffer in a low-impedance drive mode in which the pad pull-down transistor and the pad pull-up transistor are biased to selectively couple the pad terminal to a ground supply terminal and a power supply voltage, respectively; operating the tri-state buffer in a high-impedance, tri-state mode in which the pad pull-up and pad pull-down transistors are biased in an off state; coupling a voltage on the pad terminal to a well terminal of the pull-up voltage protection transistor through a feedback path when the tri-state buffer is in the high-impedance, tri-state mode and the voltage on the pad terminal exceeds a selected voltage level; and decoupling the voltage in the pad terminal from the well terminal of the pull-up voltage protection transistor through the feedback path when the tri-state buffer is in the high-impedance, tri-state mode and the voltage on the pad terminal is less than the selected voltage level.
Another aspect of the present invention relates to a method of maintaining an output driver stage of a tri-state buffer in a high-impedance tri-state mode when the voltage on the pad terminal of the buffer exceeds a selected voltage. The outputs driver stage includes a pad pull-up transistor which is coupled to the pad terminal in series with a pull-up protection transistor. The method includes: coupling the voltage on the pad terminal to a well terminal and a control terminal of the pull-up voltage protection transistor when the tri-state buffer is in the high-impedance tri-state mode and the voltage on the pad terminal exceeds the selected voltage; coupling the well terminal of the pull-up voltage protection transistor to a power supply terminal when the voltage on the pad terminal is less than the selected voltage; and coupling the control terminal of the pull-up voltage protection transistor to a ground supply terminal when the tri-state buffer is in the low-impedance drive mode.
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Sedra et al., “Microelectronic Circuits & Devices”, Prentice Hall, p. 343.
Eklund Eric W.
Schmitt Jonathan A.
Cho James H.
LSI Logic Corporation
Tokar Michael
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