Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1998-09-24
2002-04-16
Williams, Alexander O. (Department: 2926)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S784000, C257S048000, C257S780000, C257S775000, C257S773000, C257S692000, C438S017000, C438S018000, C324S754090, C324S755090, C324S537000, C324S701000, C361S772000, C361S760000
Reexamination Certificate
active
06373143
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a structure and method for testing integrated circuit devices, and more particularly, to a structure and method for performing failure analysis on an integrated circuit.
BACKGROUND ART
The ability to perform failure analysis on integrated circuit (IC) devices is an important aspect of ensuring quality during the ongoing development life cycle of an IC. The process of analyzing faults may need to occur anywhere from early design stages of an IC right through to a point where an end user discovers a failure. Once the reason for the failure is detected, the IC design can be modified in order to correct the problem.
The process of performing fault analysis on an IC typically requires the removal of at least a portion of the packaging that makes up the IC device in order to expose the necessary electrical components. One of the most common IC packages includes the use of a chip carrier or lead frame to hold the much smaller chip or die, which contains the functional circuitry. Electrical connections between the chip and lead frame are typically accomplished with a wire bonding system where wires, typically formed of gold or aluminum, connect wire bond pads on the chip to metal pads on the lead frame.
FIGS. 1 and 2
depict a chip
10
having pads
12
for receiving a wire
16
. It can be seen that a first end of the wire
16
is formed into a ball or wire bond
14
that is bonded to pad
12
. Once these connections have been made, the exposed area is encapsulated into a final product. In performing fault analysis on IC's using lead frame packaging, the encapsulated area must be removed in order to expose the chip pads
12
.
Once the chip pads
12
are exposed, probes can be set in contact with the pads
12
in order to determine the cause of the failure. Unfortunately, an initial polishing step must be performed in order to remove most of the wire
16
and wire bond
14
from the pad
12
. Without this removal step, it is very difficult to position the required number of probes in place. Furthermore, if the wire
16
and wire bond
14
are left in place, the probe would not directly contact the pad
12
, and therefore potentially cause a faulty test result. Accordingly, under previous fault isolation techniques, it has been necessary to remove the ball bonds before attempting to probe for failures.
Unfortunately, in addition to adding an extra step, the removal of the wires and wire bonds from the chip limits the type and extent of testing that can be performed. For example, connections on and between chip pads cannot be verified. Thus, without an improved structure and method for performing fault analysis, the deficiencies of the prior art will remain.
SUMMARY OF THE INVENTION
The present invention overcomes the deficiencies of the prior art by including a structure and method for providing chips with probe pad extensions in electrical communication with the chip's pads. Accordingly, during a failure analysis process, probing can occur without removing the wire and/or wire bond from the pads on the chip surface. The invention therefore provides an integrated circuit comprising a plurality of conductive pads having a first area for receiving a wire bond and a second area for receiving a probe, wherein the second area abuts, and is in electrical communication with the first area.
In addition, a method for forming an integrated circuit device having wire bond pads that are easily probed is provided and comprises the steps of: (1) creating each wire bond pad within a single layer of the integrated circuit device during a fabrication process; and (2) forming each wire bond pad with a first area for receiving a wire bond and a second area for receiving a probe, wherein the first and second area are integrally formed substantially simultaneously, and wherein the first and second areas are in electrical communication with each other.
Finally, a method is provided for performing failure analysis on an integrated circuit after packaging is completed and a fault has been detected, wherein the integrated circuit comprises wire bond pads each having a pad extension formed adjacent to a portion of the pad having a wire bond, wherein the method comprises the steps of: (1) removing a portion of a lead frame packaging to expose the wire bond pads; and (2) probing the pad extension of at least one of the wire bond pads with the wire bond remaining affixed to the at least one wire bond pad.
It is therefore an advantage of the present invention to provide a system for more easily performing tests on an integrated circuit device.
It is therefore a further advantage of the present invention to provide a system for performing more robust tests on an integrated circuit device.
It is therefore a further advantage of the present invention to provide a system for performing failure analysis tests without removing wires and wire bonds from the pads of a chip.
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Schmeiser Olsen & Watts
Walter, Jr. Howard J.
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