Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-02-07
2003-05-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06560753
ABSTRACT:
The present invention generally relates to integrated circuits, and more particularly, to an integrated circuit having tap cells located at equally spaced intervals and to a method for positioning tap cells at equally spaced intervals in an integrated circuit.
Undesired bipolar transistors are inherently formed in integrated circuits that are manufactured using conventional integrated circuit manufacturing techniques. These undesired bipolar transistors may cause the integrated circuit to have robustness problems including, for example, a phenomenon known as latch-up. Latch-up occurs when the undesired bipolar transistors in combination with desired transistors create a positive feedback circuit in which the current flowing through the circuit increases to a magnitude that exceeds the current capacity of the integrated circuit. The excess current causes the integrated circuit to become defective and thus, unusable.
As is well known in the art, latch-up is prevented by placing well taps and substrate taps at positions in the integrated circuit that are located appropriate distances from one another. Each well tap is an electrically conductive lead that couples a well region of the integrated circuit to a power source and each substrate tap is an electrically conductive lead that couples a substrate region of the integrated circuit to ground. Coupling the well and substrate regions to power and ground, respectively, reduces the substrate resistance, thus causing the positive feedback to be removed.
In particular, the taps must be positioned so that the distance between any two well taps and any two substrate taps does not exceed a maximum allowable distance that is obtained using a set of design rules associated with the integrated circuit. As will be understood by one having ordinary skill in the art, the design rules typically specify that the distance from any point in either the substrate or well regions must not be located farther than a maximum distance from the nearest substrate tap or well tap, respectively. Thus, the maximum allowable distance specified in the design rules is not defined as being equal to the maximum allowable distance as that term is used for purposes of this discussion, i.e., the maximum allowable distance between tap cells. Rather, the maximum allowable distance between tap cells is equal to the maximum distance specified in the design rules multiplied by a factor of two. As is well known in the art of integrated circuit design, the design rules may also specify various other physical parameters necessary for the proper construction of the integrated circuit such as, for example, the minimum allowable distance between wires or conducting paths disposed in the integrated circuit and the minimum allowable width of such wires.
Currently, methods for positioning well and substrate taps in an integrated circuit are performed during the circuit design process which begins with defining the desired functions or computing tasks to be performed by the integrated circuit. These functions, once defined, are described in a hardware description language that is then translated by hand or using a computerized synthesis tool, into a netlist. As will be understood by one having ordinary skill in the art, a netlist defines a set of logic gates and the connectivity between the logic gates needed to implement the functions described in the hardware description language. For example, the netlist may include a list of the logic gates, wires and input/output ports needed to implement the integrated circuit. After the netlist has been created, the integrated circuit designer provides the netlist and a floorplan as data input to a computerized “place and route” tool that creates a layout associated with netlist. The floorplan specifies various physical constraints associated with the integrated circuit design including, for example, the location of the power grid, the locations of input and output ports and the locations where the various wires or conducting paths will be located. The “place and route” tool uses the netlist and floorplan to determine the physical design of the integrated circuit from which the integrated circuit will ultimately be fabricated. Each logic gate is represented in the netlist by a logic cell and thus, the resulting layout is comprised of a set of logic cells that, when formed in the integrated circuit, will implement the logic dictated by the corresponding logic gates. To reduce the time required to perform the design process, cell libraries have been created wherein standard cell designs are available. Of course, there are applications that may require one or more specialized cells in which case the designer will either create a custom cell for the layout or alter a library cell in a manner required by the desired design. Once complete, the resulting layout is used to manufacture the desired integrated circuit.
Two well-known methods for positioning taps in an integrated circuit occur at different stages of the circuit design process. In a first tap positioning method, the positions of the taps were determined by virtue of using a standard cell library for cell selection. More particularly, each standard cell, also referred to as a library cell, was designed to include at least one well tap and one substrate tap. Thus, when the “place and route” tool used the netlist to extract standard library cells to use for the layout, the tap locations were defined in the resulting layout by default. This technique of placing at least one of each type of tap per library cell was effective for earlier-generation integrated circuits because earlier integrated circuits and the cells associated with these integrated circuits were physically larger than the integrated circuits of today. More particularly, at least one well tap and one substrate tap had to be placed in each library cell to satisfy the design rule related to the maximum allowable distance between taps. In some instances, the dimensions of a cell must be increased in order to fit the taps thereby causing an undesired increase in the size of the integrated circuit.
In a second tap positioning method, a layout was prepared using cells that are not designed to include taps and then proper locations for the taps were determined by engineers. Although this second method yielded the optimal result for layout density, it was extremely costly in terms of engineering hours. Using this method, an engineer determined appropriate locations for a set of taps and then used a design rule checker to determine whether the taps were indeed appropriately positioned, i.e., are in compliance with the design rules. As is well known in the art, a design rule checker is a computer-aided design tool that determines whether the resulting layout complies with the design rules associated with the integrated circuit. These steps were then repeated in an iterative fashion until the resulting measurements indicated that the tap locations had been properly positioned. Unfortunately, the iterative and manual nature of the process caused it to be a time consuming and thus costly task.
However, due to continuing developments in the design and manufacture of integrated circuits, cell dimensions are shrinking. As a result, a well tap and a substrate tap are no longer required in each cell and the engineering hours spent positioning taps in library cells are needlessly spent. Moreover, the positioning of unnecessary taps needlessly consumes the area of the cell that may otherwise be available for other cell circuitry and further consumes the area available for wires in the cell.
REFERENCES:
patent: 5987086 (1999-11-01), Raman et al.
Barney Clive Alva
Grange Scott Ryan
Bowers Brandon
Siek Vuthe
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