Integrated circuit having sacrificial spacers for producing grad

Details Integrated circuit having sacrificial spacers for producing grad Integrated circuit having sacrificial spacers for producing grad

1996-12-06

1999-02-09

Whitehead, Jr., Carl W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257340, 257344, H01L 2701, H01L 2976

Patent

active

058698663

ABSTRACT:
An integrated circuit is formed whereby junctions of NMOS transistors are formed dissimilar to junctions of PMOS transistors. The NMOS transistors include an LDD area, at least one MDD area, and a heavy concentration source/drain area. Conversely, the PMOS transistor includes an LDD area and a source/drain area. The NMOS transistor junction is formed dissimilar from the PMOS transistor junction to take into account, inter alia, the less mobile nature of the junction dopants relative to the PMOS dopants. Thus, a lessening of the LDD area and the inclusion of an MDD area provides lower source-drain resistance and higher ohmic connectivity in the NMOS device. The PMOS junction includes a relatively large LDD area so as to draw the highly mobile, heavy concentration boron atoms away from the PMOS channel.

REFERENCES:
patent: 4818715 (1989-04-01), Chao
patent: 5241203 (1993-08-01), Hsu et al.
patent: 5663586 (1997-09-01), Lin

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