Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-04-25
2004-04-06
Tran, Michael (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S226000
Reexamination Certificate
active
06717869
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated circuit architecture and method of production for improving the percentage yield of good components.
BACKGROUND OF THE INVENTION
It is known that defects randomly spread over the area of a semiconductor wafer cause a chip (or integrated circuit) having such defects that is removed from the wafer during the manufacturing process to be rejected upon test. A percentage of good integrated circuits out of total number manufactured in the wafer is referred to as the yield. Typically, defects are spread evenly over the area of semiconductor wafer and are characterized by so-called defect density, which varies as a function of manufacturing process maturity, process geometry, sensitivity, chip density, and so on. For example, the finer the process geometry, the lower is the yield per unit area; the more sensitive the integrated circuit is to process variance, the lower is the yield. Likewise, yield decreases as the integrated circuit density increases. For this reason, memory areas have lower yield than logic areas, since the memory cell is the densest element of the integrated circuit.
As a result, as the size and density of an integrated circuit increase, the probability of a defect being found on the integrated circuit becomes higher, and this results in fewer integrated circuits being serviceable after manufacture. This increases the cost of a good integrated circuit, since it needs to cover the cost of those many others with defects.
Moreover, high performance integrated circuits required for Very Large Scale of Integration (VLSI) (high capacity memory devices), or those required for powerful processing (multi-processor arrays) are very expensive, regardless of yield considerations. However, their per-unit price clearly increases even more as yield falls.
It is known to provide integrated circuits containing memory chips with redundant memory cells so as to allow external testing, whereby the memory array is tested so as to identify faulty memory components and to replace these with functional components.
For example, U.S. Pat. No. 5,313,424 entitled “Module level electronic redundancy” discloses a redundancy system formed on a semiconductor chip, which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.
U.S. Pat. No. 6,011,748 entitled “Method and apparatus for built-in self test of integrated circuits providing for separate row and column addresses” discloses a BIST (Built-In Self-Test) function in which both the row address and the column address of a memory to be tested may be selected independently. Addresses to be tested may be selected flexibly so as to improve transition time between rows, allowing determination of which memory address passes or fails the test.
In order to improve the yield of VLSI integrated circuits (ICs), different techniques of redundant manufacturing are used for very high integration level of memory devices. Such techniques as described, for example, in above-mentioned U.S. Pat. Nos. 5,313,424 and 6,011,748, provide for ICs to be manufactured with spare memory cells, which, in turn, replace defective ones, either during integrated circuit testing (permanently) or during built-in self test (BIST) operation (on-the-fly). However, no techniques have been proposed so far to extend this concept to multi-processor ICs.
It would clearly be an advantage to provide a multi-processor integrated circuit where self-testing is an inherent feature of the chip's architecture that may be used both to increase yield and also reliability of the integrated circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a multi-processor integrated circuit where self-testing and self-organization are inherent features of the chip's architecture.
This object is realized in accordance with a first aspect of the invention by a method for increasing the yield and/or reliability of an integrated circuit having a common circuit, said method comprising:
(a) connecting to the common circuit a plurality of mutually redundant clusters each having a respective processing unit and associated auxiliary components, and
(b) self-testing the respective processing unit in each cluster, and
(c) disconnecting a faulty or unresponsive cluster from the common circuit SO that failure of one cluster does not cause failure of the integrated circuit.
According to a second aspect of the invention, there is provided an integrated circuit architecture comprising:
a common circuit including a system controller and a data bus coupled to a plurality of redundant processing units, or clusters, each adapted to perform self-diagnosis and to report a status thereof to the system controller via a status line;
said system controller being adapted to disconnect a faulty or unresponsive cluster from the common circuit in order to allow normal operation of remaining operative components.
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D.S.P. Group Ltd.
Nath & Associates PLLC
Tran Michael
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