Integrated circuit having polyimide/metal passivation layer and

Details Integrated circuit having polyimide/metal passivation layer and Integrated circuit having polyimide/metal passivation layer and

1987-11-02

1989-05-02

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156652, 156655, 1566591, 156668, 357 71, 430313, 430317, 437203, 437235, H01L 2348, B44C 122, B29C 3700

Patent

active

048273260

ABSTRACT:
This process uses a metal lift-off step and results in a layer of polyimide covering the surface of an integrated circuit, except at the bonding pads which are covered by metals. A layer of polyimide is applied to the surface of an integrated circuit and then partially cured. A layer of positive photo-resist is applied over the polyimide layer and then pattern exposed and developed, resulting in windows being opened up over the bonding pads of the integrated circuit. The remaining photo-resist is then flood exposed. One or more metals are then sputtered over the resist and the bonding pads. The integrated circuit is then immersed in solvent and the remaining layer of photo-resist, including the metal above it, is lifted-off. Only the metal over the bonding pads remains. The polyimide layer is then fully cured.

REFERENCES:
patent: 4113550 (1978-09-01), Saiki et al.
patent: 4152195 (1979-05-01), Bahrle et al.
patent: 4378383 (1983-03-01), Moritz
patent: 4411735 (1983-10-01), Belani
patent: 4560436 (1985-12-01), Bukhman
Dillinger et al., Enhanced Via Etch Procedure for Silicon Nitride-Polyimide, IBM Tech. Disc. Bulletin, vol. 27, No. 2, Jul. 1984, pp. 1041-1043.
"Tape Automated Bonding Process for High Lead Count LSI", 1983 IEEE Publication 0569-5503/83/0000-0221, pp. 221-225.

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