Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2002-08-19
2004-06-08
Le, Dung A. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S739000, C257S758000, C361S762000, C361S767000, C361S780000, C438S612000, C438S917000
Reexamination Certificate
active
06747352
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor packaging, and more specifically, to a substrate having multiple connections to external terminals for providing electrical inter-connection between multiple power connections of one or more integrated circuit dies to a single external terminal.
BACKGROUND OF THE INVENTION
Semiconductors and other electronic and opto-electronic assemblies are fabricated in groups on a wafer. Known as “dies”, the individual devices are cut from the wafer and are then bonded to a carrier. The dies must be mechanically mounted and electrically connected to a circuit. For this purpose, many types of packaging have been developed, including “flip-chip”, ball grid array and land grid array among other mounting configurations.
High-density interconnect schemes such as high-density ball grid arrays (BGAs) or land grid arrays (LGAs) typically have multiple power and ground balls or lands in the array in order to provide a low impedance connection from the die(s) to the external power supply connections. Multiple terminals are also used to provide improved heat transfer from the semiconductor die(s) to the mounting carrier (e.g., printed circuit board or socket). In one terminal arrangement of these packages, the entire center section of the array is dedicated to power and ground connections.
The thermal and electrical impedances of the terminal (e.g., solder ball or land) do not necessitate the multi-terminal connection arrangement. Rather, it is the impedance of the wire-bonding structure (if used) and the impedance of the circuit traces on the substrate that necessitate the use of multiple terminals.
Therefore, it would be desirable to provide a method and integrated circuit package having a reduced number of power and ground terminals, while maintaining a low electrical impedance and a low thermal impedance connection from the integrated circuit die(s) to ground and power supply terminals. It would similarly be desirable to provide a method and integrated circuit package providing a higher-density interconnect by reducing the number of required power and ground connections.
SUMMARY OF THE INVENTION
A substrate having multiple power supply and/or ground connections between one or more die terminals to a single external pad provides a lower pin count or higher-density interconnect integrated circuit package. The integrated circuit includes at least one integrated circuit die, a substrate for mounting and electrically interconnecting the integrated circuit die(s) and a cover for covering the integrated circuit die(s).
The substrate includes multiple terminal pads for connection to external terminals of the integrated circuit and multiple bond pads for connection to terminals of integrated circuit die(s) where at least two power and/or ground connections from among bond pads are connected to a single terminal pad.
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Hiner David Jon
Huemoeller Ronald Patrick
Rusli Sukianto
Amkor Technology Inc.
Le Dung A.
Weiss, Moy & Harris P.C.
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