Integrated circuit having memory with configurable...

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S226000, C365S189020

Reexamination Certificate

active

07903483

ABSTRACT:
An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.

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Non-Published U.S. Appl. No. 11/847,424 filed with the US Patent Office on Aug. 30, 2007, first named inventor Matthew S. Berens.
Notice of Allowance dated Sep. 9, 2010 in U.S. Appl. No. 12/388,911.

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