Static information storage and retrieval – Read/write circuit – Testing
Patent
1998-02-26
1999-08-03
Phan, Trong
Static information storage and retrieval
Read/write circuit
Testing
371 211, 3241581, G11C 700, G11C 2900
Patent
active
059333782
ABSTRACT:
An integrated circuit is described which includes a test mode circuit that allows a substrate of the integrated circuit to be forced to a voltage level dictated by an external connection during a test operation, and provides an improved substrate isolation from the external connection during non-test operations. Both n-channel transistor and p-channel transistor isolation circuit embodiments are described. An integrated circuit memory device is described which incorporated the test mode and isolation circuits. The external connection can be coupled to a negative voltage during non-test operation which is more negative than a threshold voltage below a substrate voltage without inadvertently coupling the external connection and substrate together.
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Devereaux Kevin
Gans Dean
Micro)n Technology, Inc.
Phan Trong
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