Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1999-07-27
2002-05-14
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C324S1540PB
Reexamination Certificate
active
06388926
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to integrated circuits with substrate isolation circuitry.
BACKGROUND OF THE INVENTION
Many types of integrated circuits employ on-chip substrate bias generators (also known as “charge pumps”) for enhanced performance by lowering the junction capacitance between diffused areas and the substrate, and by reducing the body effect on integrated field-effect transistors (“FETs”). Charge pumps are typically used on complimentary metal-oxide semiconductor (“CMOS”) memory circuits such as static random-access memories (“SRAMs”) and dynamic random-access memories (“DRAMs”), but are not limited to these applications.
Referring now to
FIG. 1
, a simplified block diagram of a packaged integrated memory circuit
10
includes a package
12
, external package pins
14
, and dedicated package pins
16
,
18
,
20
, and
22
. External package pins
14
typically provide electrical connection for address buses and control functions for the memory. Pin
16
provides electrical connection to a first power supply voltage VCC, pin
18
provides electrical connection to a second power supply voltage VSS, pin
20
receives an inverted chip select signal, and pin
22
receives an inverted output enable signal. Pins
14
-
22
are only shown as being representative of atypical memory circuit but other varied configurations are possible. It is important to note that the substrate is not connected to any of the external package pins.
Inside the package, the integrated circuit includes a primary memory circuit
26
, a charge pump
24
, and a substrate
28
. The charge pump
24
and memory circuit
26
are integrated together in a single integrated circuit, which is in physical and electrical contact with the substrate
28
. Conductors
30
and
32
are shown only to illustrate the substrate voltage. The charge pump
24
is powered by VCC and VSS and generates a−1 volt VBB voltage for driving the substrate. In turn, the entire substrate is biased to−1 volts, including the portion underlying the memory circuit
26
.
Integrated circuit memory circuits are typically tested at wafer sort where, since the integrated circuit has not yet been packaged, the substrate can be readily electrically contacted. During testing, the positive power supply voltage VCC and the substrate voltage VBB are varied in order to stress certain failure mechanisms and identify both failed and marginally performing circuits. Once the integrated circuits are packaged, however, access to the substrate is lost and the ability to stress failure mechanisms related to the substrate voltage is diminished. U.S. Pat. No. 5,212,422, incorporated herein by reference, describes a circuit for forcing the internal substrate voltage VBB once the integrated circuit has been packaged to allow more thorough testing. A portion of U.S. Pat. No. 5,212,422 is provided in the following paragraphs.
Referring to
FIG. 2
, a forcing circuit is shown for forcing an integrated circuit substrate to ground. The forcing circuit of
FIG. 2
is manufactured on an integrated circuit together with a primary circuit such as DRAM or SRAM. The integrated circuit is fabricated in a package having a number of external pins in electrical contact with the primary circuit and forcing circuit, but none of the external pins are connected with the integrated circuit substrate. The forcing circuit includes a test mode indicator or detector circuit
34
having an input coupled to an external primary circuit pin
14
and an output for providing a test mode signal TESTMODE* on conductor
38
. An N-channel switching transistor Q
3
has a drain coupled to the substrate
36
, a source coupled to ground, and a gate for receiving the test mode signal VBBTEST, which is logically inverted from TESTMODE*. The TESTMODE* signal is inverted by an inverter stage including a P-channel transistor Q
1
and an N-channel transistor Q
2
.
In the forcing circuit of
FIG. 2
, the test mode detector
34
can be a supervoltage detector responsive to a boosted type of digital or analog circuit that responds to a combination of inputs not normally allowed during normal operation of the integrated circuit. For example, in a DRAM, applying a CAS* (column address strobe) input signal before a RAS* (row address Strobe) input signal while holding the WE* (write enable) signal low is a sequence that is not encountered or allowed during normal operation. An electronic key circuit can be designed by those skilled in the art to provide a TESTMODE* signal in response to this sequence of input signals. Other types of test mode detector circuits can be designed that recognize an externally applied signal or signals requesting the forced-substrate test mode.
An alternative forcing circuit that allows connection of any negative voltage to the substrate is shown in FIG.
3
. The forcing circuit includes a test mode detector
34
and a switching transistor Q
8
for connecting the substrate
36
to a predetermined voltage through an external pin
44
. The substrate voltage can be connected to any arbitrary negative voltage. The forcing circuit includes a test mode detector circuit
34
having an input coupled to an external primary circuit pin and an output for providing complementary test mode signals TESTMODE and TESTMODE* on conductors
38
and
39
. An N-channel switching transistor Q
8
has a drain coupled to the substrate
36
, a source coupled to the external pin
44
, and a gate for receiving the test mode signal VBBTEST, which is logically inverted from TESTMODE*.
Additional circuitry includes P-channel transistors Q
4
and Q
5
, as well as N-channel transistors Q
6
and Q
7
to form a positive feedback amplifier for controlling the switching action of transistor Q
8
, as well as the generation of the VBBTEST signal for disabling the on-chip charge pump, if desired. The gates of transistors Q
4
and Q
5
respectively receive the TESTMODE and TESTMODE* signals, the sources being coupled to the five volt VCC power supply. The drains and cross coupled gates of transistor Q
6
and Q
7
are respectively coupled to the drains of transistor Q
4
and Q
5
. The coupled drains of transistors Q
5
and Q
7
are coupled to the gate of transistor Q
8
and form the VBBTEST signal on conductor
40
. The sources of transistors Q
6
and Q
7
are coupled to the substrate
36
.
In operation, the forcing circuit of
FIG. 3
allows connection of any negative voltage to the substrate
36
through external pin
44
during a test operation. During normal operation TESTMODE* is at a logic high state and TESTMODE is at a logic low state. Transistor Q
4
is on and circuit node
42
is at a logic high state. Transistor Q
7
is also on and effectively connects the gate of switching transistor Q
8
to the substrate
36
. During normal operation, the voltage on the substrate
36
is about−1 volts and therefore switching transistor Q
8
is off. Assuming that a voltage on external pin
44
is not a threshold voltage below the gate voltage of Q
8
, the external pin
44
is electrically isolated from the substrate
36
. During the substrate-forcing test mode, TESTMODE is at a logic high state and TESTMODE* is at a logic low state. Transistor Q
5
turns on, which brings VBBTEST high and turns on transistor Q
8
. Transistor Q
6
is also turned on, which brings node
42
to the substrate potential. Thus, transistor Q
7
is turned off, and the substrate
36
and the external pin
44
are electrically coupled together.
A problem with the circuitry of
FIG. 3
is electrical isolation of the substrate during normal non-test mode operation. Because external connection
44
is used during operation of the integrated circuit, over-shoot and under-shoot signal voltages can be experienced. An under-shoot voltage which is a threshold voltage (Vt) below the gate of Q
8
can couple the substrate to pin
44
and adversely effect the substrate voltage. For the reasons stated above, and for other reasons stat
Devereaux Kevin
Gans Dean
Phan Trong
Schwegman Lundberg Woessner & Kluth P.A.
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