Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
1999-05-24
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S189090, C365S230060
Reexamination Certificate
active
06219270
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to an integrated circuit with a matrix of dynamic memory cells.
BACKGROUND OF THE INVENTION
Dynamic memory stores information as charge in a memory capacitor. In embedded memory (memory included in an integrated circuit with logic circuits, usually for storing data for specific logic functions) the memory capacitor is often implemented as a field effect transistor, the control electrode of this transistor forming one terminal of the capacitor and the drain and source of this transistor forming the other terminal of the capacitor.
Charge is supplied to the capacitor via an access transistor. When information is written the access transistor connects one of the terminals to the positive supply voltage or to the negative supply voltage, dependent on the information value that must be written. The other terminal of the capacitor is kept in connection with a plate conductor, which is at a substantially fixed voltage level.
The retention time of this information is limited by leakage currents, which over time efface the difference between charges that are used to represent different information values. The retention time can be improved by increasing the charge difference between the different charges that represent different information values.
The charge difference is limited amongst others by a threshold voltage drop across the access transistor. In case a field effect transistor is used as capacitor, the charge difference is also limited the minimum charge that is required to keep the channel of this field effect transistor conductive.
It is known to boost the voltage at the plate conductor so that the field effect transistor operates as a capacitor over a wider voltage range, thus increasing the charge difference. It is also known to boost a voltage at the control electrode of the access transistor outside a supply voltage range of the memory. This has the effect of overcoming the threshold voltage drop, thus also increasing the charge difference.
Boosting the voltage at the control electrode of the access transistor requires a strong and fast access transistor control circuit. The speed with which the control electrode can be driven strongly influences the access speed of the memory. Usually the control electrodes of a row of access transistors in a memory matrix are driven in parallel. This means that the access transistor control circuit must be able to drive the control electrodes of a row of access transistors quickly. As a result, the access transistor control circuit may be quite large.
SUMMARY OF THE INVENTION
Amongst others, it is an object of the invention to provide for an integrated circuit with a memory that requires a small control circuit for the control electrode of the access transistors.
The integrated circuit according to the invention has a switching element connected between the control electrode of the access transistor and the cell plate conductor. The cell plate conductor is connected to the capacitors of a matrix of memory cells. The voltage of the cell plate conductor is boosted. When the switching element is made conductive, the control electrode of the access transistor is driven from the cell plate conductor. This is a very strong driver, because the cell plate conductor has a large capacitance from which to draw charge for the control gate of the access transistor. The capacitance of the cell plate conductor is large because of the size of the cell plate conductor needed to connect all the capacitors and because of the large number of capacitors of the matrix connected to the cell plate conductor.
In an embodiment of the integrated circuit according to the invention a PMOS transistor is used as access transistor. In this embodiment, the voltage of the plate conductor is boosted below the negative power supply voltage. This means that the PMOS transistor will remain conductive even if the voltage supplied to its main current channel is at the negative power supply level. In this embodiment, the voltage of the plate conductor is regulated relative to the positive power supply voltage, so that the difference between the voltage of the plate conductor and the positive power supply voltage is substantially independent of the difference between the positive and negative power supply voltages.
The integrated circuit has to be able to work with a supply voltage difference in a standard tolerance range. The voltage of the plate conductor has to be limited so that the gate oxide of the PMOS access transistor does not break down at any position in the tolerance range. If the difference between the negative supply voltage and the voltage of the plate conductor were fixed, this would mean that this difference should be quite small, so as to account for the highest possible positive supply voltage in the tolerance range. As a result, there would be little improvement when the positive supply voltage is at the minimum of the tolerance range.
By regulating the voltage difference between the voltage of the plate conductor and the positive supply voltage to a supply voltage independent value, a bigger improvement can be realized over the entire supply tolerance range. In this case the maximum acceptable voltage difference between the plate conductor and the positive supply can be used over the entire supply tolerance range.
REFERENCES:
patent: 5317532 (1994-05-01), Ochii
patent: 5532953 (1996-07-01), Ruesch et al.
patent: 5694355 (1997-12-01), Skjaveland et al.
patent: 5870329 (1999-02-01), Foss
Van Der Sanden Cornelis G. L. M.
Van Geloven Johannes A. J.
Biren Steven R.
Ho Hoai V.
Nelms David
U.S. Philips Corporation
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