Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1998-09-29
2001-07-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S098000, C326S093000, C326S095000, C326S083000, C326S121000
Reexamination Certificate
active
06255853
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of integrated circuits, and more particularly to an integrated circuit having dynamic logic with reduced standby leakage current.
BACKGROUND OF THE INVENTION
Domino logic stages are used in integrated circuits to provide high-speed logic functionality. In general, domino logic involves the charging of dynamic nodes during a precharge phase. Subsequently, during an evaluation phase, inputs are fed to the logic stage which may or may not evaluate to provide a path to the low voltage supply from one or more of the dynamic nodes. The dynamic nodes represent a logic high or a logic low depending on whether or not a path to the low voltage supply is formed. Generally, the dynamic node is connected to the input of a static gate (e.g., an inverter), and the output of the static gate is input to other dynamic gates. In this manner, logic can propagate through successive dynamic logic stages. Because high logic levels are precharged, the logic evaluation period is reduced in time. Active power in a domino or dynamic logic block can be reduced by slowing or stopping the clock, but leakage currents in the dynamic and static portions of the dynamic logic section will persist and contribute to power consumption.
One problem that can occur with domino logic is that current leakage can occur through connected logic gates during the precharge phase or other standby period. For example, where each dynamic node feeds an inverter, there can be leakage through transistors within the inverter during the period of time that the dynamic node is precharged high. With the input to the inverter at a logic high, leakage can occur, for example, through the inverter's P-channel transistor which is coupled to the high voltage supply. This leakage is particularly problematic where inverters or other logic gates employ low threshold voltage transistors in order to provide higher speed operation. The low threshold voltage transistors experience higher leakage current for a given gate voltage, thus they cause more of a problem.
One conventional solution to the problem of leakage current is to avoid using low threshold voltage transistors where problems occur. Thus, for example, a high threshold voltage P-channel transistor can be used in an inverter to avoid leakage current. Another conventional solution is to shut off power to an entire dynamic logic section including the dynamic gates and associated static logic gates to avoid any leakage current from that section. However, these conventional solutions suffer from problems in that it is undesirable to use high threshold voltage transistors, and it is undesirable to recharge all the dynamic nodes every time the power supply is turned back on. For example, if a dynamic node and the output of the associated static gate both go low in standby, one or the other will have to be recharged high in restart.
SUMMARY OF THE INVENTION
In accordance with the present invention, an integrated circuit having dynamic logic with reduced standby leakage current is provided that provides advantages over conventional dynamic logic circuits.
Knowledge of the state of the dynamic node and its associated static logic gate in relation to the clock signal or standby condition is used to selectively include a first transistor between the dynamic logic gate and a first voltage supply and/or include a second transistor between the associated static gate and a second voltage supply.
In accordance with one aspect of the present invention, an integrated circuit is disclosed that has a dynamic logic stage with reduced standby leakage current. The integrated circuit includes a logic gate coupled to a dynamic node of the dynamic logic stage. The logic gate has a first voltage supply terminal and a second voltage supply terminal. The logic gate consumes standby leakage current when the dynamic logic stage is not in an evaluation phase or when the clock is idle. A transistor has a source connected to a first voltage supply, a drain connected to the first voltage terminal of the logic gate, and a gate connected to a control signal. The drain of the transistor provides an intermediate node for supplying voltage to the logic gate. The transistor is operable to be turned off by the control signal when the dynamic logic stage is not in an evaluation phase or the dynamic logic section is in standby such that the transistor reduces the standby leakage current of the logic gate. In addition, a sub-circuit, such as a transistor, can be used to limit a voltage difference between the high voltage supply and a voltage level of the intermediate node.
According to another aspect of the present invention, the standby leakage current of a dynamic logic stage is reduced. A first transistor used to enable the dynamic logic stage has a drain connected to the dynamic logic stage, a source connected to an intermediate node and a gate connected to a clock signal for the dynamic logic stage. A second transistor has a source connected to a first voltage supply, a drain connected to the intermediate node, and a gate connected to a control signal such that the intermediate node provides a first voltage supply for the dynamic logic stage. The second transistor is operable to be turned off by the control signal when the dynamic logic stage is not in an evaluation phase or when the dynamic section is in standby. The second transistor thereby reduces the standby leakage current of the dynamic logic stage. In addition, a sub-circuit, such as a transistor, can be used to limit a voltage difference between the first voltage supply and a voltage level of the intermediate node.
A technical advantage of the present invention is the ability to have a dynamic node feeding a static logic gate and reduce leakage current through the static logic gate by including a transistor between the logic gate and the voltage supply. In particular, a P-channel transistor can be used in series between an inverter and a positive power supply, V
DD
, and controlled in order to shut off leakage current with little degradation of performance.
Another technical advantage of the present invention is the limiting of a voltage difference between a power supply and an intermediate node supplying logic gates such that start-up does not require significant charging of nodes within the dynamic logic. In particular, a keeper transistor can be connected to the intermediate node to keep it from dropping too low and to allow fast start-up for the dynamic logic stage.
REFERENCES:
patent: 4859870 (1989-08-01), Wong et al.
patent: 5525916 (1996-06-01), Gu et al.
patent: 5838170 (1998-11-01), Schorn
patent: 5880609 (1999-03-01), Klass et al.
patent: 6002271 (1999-12-01), Chu et al.
Brady III Wade James
Tan Vibol
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tokar Michael
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