Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-08-12
2001-07-24
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S453000, C438S637000, C438S691000, C438S769000
Reexamination Certificate
active
06265294
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits (ICs) and a method of fabricating integrated circuits. More particularly, the present invention relates to an anti-reflective coating (ARC) layer and a contact fabrication process.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) fabrication generally requires that precisely controlled quantities of impurities be introduced into selected regions of a semiconductor substrate and that conductive, semiconductive, and insulative structures be built by selectively depositing and removing layers of material. These regions and structures are subsequently interconnected to create components and ultra-large scale integrated (ULSI) circuits. The patterns that define such regions and structures are typically created by photolithographic processes, wherein layers of photoresist material are deposited on either the substrate alone or on layers which have been grown or deposited above the substrate.
The photoresist material is selectively exposed to electromagnetic energy, such as, ultra-violet (UV) light, electrons, or x-rays, to define a pattern of photoresist material. The electromagnetic energy is transmitted through a cell or overlay material to define the pattern. The photoresist material can be negative or positive photoresist material.
An IC structure, such as, a contact, is often formed in a photolithographic process. A contact can be utilized to connect a conductive or metal layer to a gate conductor, a source, or a drain associated with a transistor formed on a substrate. Alternatively, the contact can connect two or more conductive layers, can connect to capacitive structures, or can connect to various semiconductive regions.
The formation of a contact is exemplarily described as follows. A contact can be formed after a gate structure or stack has been provided on a semiconductor substrate. The gate stack is located between a source and a drain region of a transistor. The transistor can be a flash memory transistor, a metal oxide semiconductor field effect transistor (MOSFET), or other device.
The gate stack is covered by an interlevel dielectric layer (ILDO) which isolates the gate stack from subsequent metal layers. The interlevel dielectric layer can be silicon dioxide, boron phosphosilicate glass (BPSG), or other insulative material. The interlevel dielectric layer is often planarized in a chemical mechanical polish (CMP) process and then selectively covered by photoresist material. The interlevel dielectric layer is etched in accordance with the photoresist material to form apertures for contacts.
Generally, an anti-reflective coating (ARC) layer is deposited on a top of the insulative layer before etching. ARC layers are particularly important for deep UV or i-line lithography associated with scaled-down CMOS devices and flash memory devices. The ARC layer reduces line width variations due to steps on the IC structure. (The ARC layer serves to planarize the top surface of the substrate.) The ARC layer is typically a polymer film (organic, e.g., CD11), which is highly absorbing and non-bleaching at the exposure wavelengths associated with the photolithographic process. The ARC layer absorbs most of the radiation (70-85%) that penetrates the photoresist material and, thereby, substantially reduces standing wave effects and scattering from topographical features.
One exemplary type of ARC material is silicon oxide nitride (SiON). The SiON material can be utilized as a bottom ARC (BARC) layer in a deep ultra-violet (UV) contact lithographic process. Generally, the thickness is approximately 100-500 Å. After the photoresist material is selectively removed, the SiON material layer is etched in accordance with the pattern of the photoresist material to define an aperture. The interlevel dielectric layer is etched through the aperture until the top surface of the substrate is reached.
After etching the interlevel dielectric layer, a conformal layer of conductive material, such as, tungsten (W), is deposited on top of the SiON layer and within the aperture. The tungsten material is removed from the top of the SiON layer by a tungsten polishing process (a CMP process). After the tungsten is removed, the SiON layer is removed.
Heretofore, after ARC layer removal processes, material associated with the tungsten layer and the ARC layer is not completely removed from the interlevel dielectric layer. In fact, the material from the contact and the ARC layer can generate discoloration on top of the interlevel dielectric layer. The discoloration on the interlevel dielectric layer can disrupt subsequent inspection (post-W inspection), such as, inspection by equipment manufactured by KLA Tencor. Such discoloration can prevent actual defects from being detected.
Additionally, conventional CMOS devices and flash memories can be subjected to charge gain and charge loss problems. For example, hydrogen and moisture from interlevel dielectric layers above the contact can diffuse into the gate stack. The hydrogen and moisture aggravate the charge gain and loss problem.
Thus, there is a need for ensuring that anti-reflective coatings do not interfere with KLA inspection. Further, there is a need for preventing discoloration on ILD layers from ARC and metal layers. Further still, there is a need for ensuring that the entire anti-reflective coating is removed during contact formation. Even further still, there is a need to prevent charge gain and charge loss due to hydrogen and moisture from interlevel dielectric layers.
SUMMARY OF THE INVENTION
The present invention relates to a method of fabricating an integrated circuit. The method includes steps of depositing an insulative layer over a gate stack, depositing a silicon nitride layer over the insulative layer, and depositing an anti-reflective coating layer over the silicon nitride layer. The method also includes etching the insulative layer, the silicon nitride layer, and the anti-reflective coating layer for a contact and removing the anti-reflective coating layer.
The present invention also relates to a method of fabricating a contact for an integrated circuit. The integrated circuit includes a gate stack covered by an insulative layer. The method includes depositing a silicon nitride layer over the insulative layer, depositing a silicon oxynitride layer over the silicon nitride layer, etching an aperture through the insulative layer, the silicon nitride layer, and the silicon oxynitride layer, and depositing a tungsten material in the aperture to form the contact.
The present invention even further still relates to an integrated circuit. The integrated circuit is manufactured by a method that includes the steps of depositing an insulative layer over a gate stack, depositing a silicon nitride layer over the insulative layer, depositing an anti-reflective coating layer over the silicon nitride layer, and etching the insulative layer, the silicon nitride layer, and the anti-reflective coating layer to form an aperture. The method also includes depositing a conformal conductive layer over the anti-reflective coating layer and in the aperture, and removing the conformal conductive material above the anti-reflective coating layer and the anti-reflective layer by a polishing technique, thereby leaving the conductive material in the aperture to form a contact.
REFERENCES:
patent: 5518948 (1996-05-01), Walker
patent: 5936272 (1999-08-01), Lee
patent: 6004850 (1999-12-01), Lucas
patent: 6004857 (1999-12-01), Hsiao et al.
patent: 6013582 (2000-01-01), Ionov et al.
patent: 6113140 (2000-10-01), Yu et al.
Morales Guarionex
Park Stephen Keetai
Rangarajan Bharath
Shields Jeff
Advanced Micro Devices , Inc.
Bowers Charles
Foley & Lardner
Kebede Brook
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