Integrated circuit having an on-board reference generator

Details Integrated circuit having an on-board reference generator Integrated circuit having an on-board reference generator

2001-04-27

2002-06-18

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S210130, C365S205000

Reexamination Certificate

active

06407955

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to electronic circuits, and more specifically to an integrated circuit (IC) having an on-board reference generator. For example, if the generator is on-board a memory circuit, one can activate the generator to provide an internal reference signal during a test mode of the memory circuit, and one can deactivate the generator to allow the memory circuit to receive an external reference signal during normal operation.
BACKGROUND OF THE INVENTION
Because it is generally true that the fewer signals needed to test an IC the higher and more efficient the testing throughput for a batch of the ICs, IC design engineers strive to minimize the number of signals needed to test an IC. For example, suppose that an IC tester has sixty signal probes. If each of the ICs being tested requires twenty test signals, then the tester can test three ICs at a time. If, however, each of the ICs requires twenty one test signals, then the tester can test only two ICs at a time. Thus in this example, just one extra test signal per IC decreases the testing throughput by one third. Furthermore, in the latter case, the IC tester is significantly under utilized, and thus the testing is relatively inefficient with respect to the tester, because eighteen signal probes (60-42) are unused during each test cycle.
FIG. 1
is a schematic diagram of a portion of a reduced-signal-level dynamic random access memory (DRAM) circuit
10
such as a Direct Rambus® DRAM (RDRAM®) specified by Rambus Inc. of Mountain View, Calif. The memory circuit
10
includes one or more terminals
12
0
-
12
n
for receiving digital signals S
0
-S
n
, a reference terminal
14
for receiving a reference voltage Vref, and clock terminals
16
a
and
16
b
for receiving complimentary Clock From Master signals CFM and {overscore (CFM)}, respectively. Typically, Vref is half way between the logic 0 and logic 1 levels of S
0
-S
n
, to provide symmetrical noise margins. Also, CFM and {overscore (CFM)} are typically derived from the rising and falling edges, respectively, of a single Master Clock (MC) signal (not shown) having a 50% duty cycle and the same frequency as CFM and {overscore (CFM)}. In one embodiment, the signals S
0
-S
n
have logic 0=1.8 volts (V) and logic 1=1.0V, Vref=1.4V, and CFM and {overscore (CFM)} each have a frequency of 400 megahertz (MHz).
The memory circuit
10
also includes differential input buffers
18
0
-
18
n
and
20
0
-
20
n
for converting the voltage levels of S
0
-S
n
into voltage levels that are compatible with the circuitry (not shown) internal to the memory circuit
10
. These buffers are arranged in pairs [
18
0
,
20
0
], . . . ,[
18
n
,
20
n
] for alternately sampling the signals S
0
-S
n
, respectively. Specifically, each buffer
18
receives a respective signal S on a non-inverting (+) terminal, Vref on an inverting (−) terminal, and CFM on a clock terminal
22
. Similarly, each buffer
20
receives a respective signal S on a non-inverting terminal, Vref on an inverting terminal, and {overscore (CFM)} on a clock terminal
24
. Receiving the complimentary CFM and {overscore (CFM)} signals instead of the MC signal provides the memory circuit
10
with two major advantages. First, although each buffer pair [
18
,
20
] effectively samples a respective signal S on both the rising and falling edges—and thus at twice the frequency—of MC, each buffer of the pair operates at only half this sampling rate. Furthermore, each buffer of the pair is sensitive to the same clock-edge polarity, i.e., either rising or falling, and thus all the buffers
18
and
20
can have the same circuit design. Reducing the sampling rate of and using a single design for the buffers
18
and
20
often reduces the overall design and layout complexity of the memory circuit
10
.
The memory circuit
10
also includes an IC package
21
. The terminals
12
0
-
12
n
,
14
, and
16
a
and
16
b
are disposed on the outside of the package
21
, and the buffers
18
0
-
18
n
and
20
0
-
20
n
, are disposed inside of the package
21
.
In operation, using the input-buffer pair [
18
0
,
20
0
] and the signal values given above as examples, the buffer
18
0
samples S
0
by comparing S
0
to Vref in response to the rising edge of CFM. If S
0
equals logic 0, i.e., 1.8 V, then the buffer
18
0
generates a high output-voltage level, which the circuitry internal to the memory circuit
10
interprets as a logic 0. Conversely, if S
0
equals logic 1, i.e., 1.0 V, then the buffer
18
0
generates a low output-voltage level, which the circuitry internal to the memory circuit
10
interprets as a logic 1. The buffer
20
0
samples S
0
in response to the rising edge of {overscore (CFM)}in a similar manner. The remaining input-buffer pairs [
18
1
,
20
1
], . . . ,[
18
n
,
20
n
] respectively sample S
1
-S
n
in a similar manner.
Specific examples of the memory circuit
10
are described in more detail in the Advance Information sheet for the Direct RDRAM® 128/144-Mbit (256k×16/18×32S) and in other Rambus® publications, which are available from Rambus Incorporated of Mountain View, Calif. or from the Rambus website at www.rambus.com, and which are incorporated by reference herein.
Unfortunately, one must provide Vref to the terminal
14
during testing of the memory circuit
10
so that the differential input buffers
18
and
20
will function properly. Thus, as discussed above, providing Vref as a test signal may significantly lower the testing throughput and efficiency for a batch of the memory circuits
10
.
SUMMARY OF THE INVENTION
In one aspect of the invention, an integrated circuit includes a differential amplifier having a first terminal that is operable to receive an input signal and having a second terminal. The integrated circuit also includes a reference circuit that generates a reference signal on the second terminal of the amplifier.
Therefore, during testing of such an IC, the tester can enable the on-board reference circuit to internally generate the reference signal such that the tester need not provide the reference signal. During normal operation, however, the IC can use the reference circuit to internally generate the reference signal or can receive the reference signal from an external source.


REFERENCES:
patent: 5335198 (1994-08-01), Van Bushkirk et al.
patent: 5359558 (1994-10-01), Chang et al.
patent: 5933366 (1999-08-01), Yoshikawa
patent: 5956277 (1999-09-01), Roohparvar
patent: 6288954 (2001-09-01), Manning
IEEE Micro, Richard Crisp/Rambus, Inc., 1997, “Direct Rambus Technology: The New Main Memory Standard”, pp. 18-28.
Direct RDRAM 128/144-Mbit (256Kx16/18x32s) Datasheet, Rambus, Inc./Frederick A. Ware, Aug., 1998, pp. 1-62.
Direct Rambus Technology Disclosure, Rambus, Inc., Oct., 1997, pp. 1-16.

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