Integrated circuit having a noise-reducing output stage with mut

Details Integrated circuit having a noise-reducing output stage with mut Integrated circuit having a noise-reducing output stage with mut

1994-06-21

1996-01-09

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 29, 327269, H03K 17284

Patent

active

054831776

ABSTRACT:
The invention relates to an integrated circuit, having an output stage with at least two respective output transistors, respective main current channels of which are connected in parallel between a first supply terminal and the output. A control circuit ensures that, in response to a variation in an input signal on the input, the charging of respective control electrodes of the at least two respective output transistors commences with a delay relative to one another. The peak value of the time derivative of a current output together by the at least two output transistors is thus limited. After the start of charging, a speed of charging of the control electrode of at least one of the two respective output transistors is reduced. The peak value of the time derivative of the current applied to the output by the at least one of the at least two output transistors is thus reduced.

REFERENCES:
patent: 4783601 (1988-11-01), Hartgring et al.
patent: 4789796 (1988-12-01), Foss
patent: 4959561 (1990-09-01), McDermott et al.
patent: 5013940 (1991-05-01), Ansel
patent: 5124579 (1992-06-01), Naghshineh
patent: 5216293 (1993-06-01), Sei et al.
patent: 5220208 (1993-06-01), Schenck
patent: 5231311 (1993-07-01), Ferry et al.

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