Static information storage and retrieval – Read/write circuit – Complementing/balancing
Reexamination Certificate
2011-05-24
2011-05-24
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Complementing/balancing
C365S194000, C365S210110, C365S211000
Reexamination Certificate
active
07948819
ABSTRACT:
Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.
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Henry Mathew R.
Lopata Douglas D.
McPartland Richard J.
Pham Hai Quang
Werner Wayne E.
Agere Systems Inc.
Gruzdkov Yuri
Hur J. H.
Mendelsohn Steve
Mendelsohn, Drucker & Associates P.C.
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