Integrated circuit having a high speed clock input buffer

Details Integrated circuit having a high speed clock input buffer Integrated circuit having a high speed clock input buffer

1999-09-21

2001-08-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S095000, C326S098000, C326S062000, C326S068000, C326S080000, C327S333000

Reexamination Certificate

active

06275070

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to integrated circuits, and more particularly to an integrated circuit memory having a high speed clock input buffer.
BACKGROUND OF THE INVENTION
Integrated circuit static random access memories (SRAMs) are used in a variety of applications today. In particular, high speed synchronous SRAMs are used in such applications as caches for computer systems, work stations, and the like. These cache memories provide a high speed storage of data or instructions that are likely to be reused. As integrated circuit technology has improved, microprocessors have correspondingly increased in speed and as microprocessor speed increases the access time of the SRAMs must decrease to provide efficient cache storage.
Integrated circuits (ICs) that are used in modern electrical systems must be designed to effectively and efficiently communicate between different types of devices that are powered by different voltage supplies. For example, it is not unusual for a 3.3 volt microcontroller unit (MCU), to be coupled to a 1.8 volt memory device. In order for these devices to effectively communicate with each other in an electrical design, the input and output buffers of the ICs must be able to accommodate different voltages.
As CMOS (complementary metal-oxide semiconductor) technologies migrate to higher performance, small device sizes, and lower power supply voltages, for example, 1.8 volts, the CMOS transistors cannot tolerate higher voltages, for example, more than 2.5 volts. In a high performance synchronous memory, all inputs have to endure high voltage stress and step down, or level shift, the higher voltage input signal (e.g. 3.3 volts) to the lower internal voltages (e.g. 1.8 volts). To handle the stress of higher input voltages, thicker oxide transistors are required. However, the switching speed of these thicker oxide transistors is generally slower. Also, the thicker oxide transistors have longer channel lengths and higher threshold voltages which tends to reduce their switching speed. In addition, the level shifting operation also tends the slow the speed of the input buffer.
The above issues can be illustrated with respect to FIG.
1
.
FIG. 1
illustrates a conventional input buffer circuit
10
that is currently used in the IC industry for buffering input clock signals for a synchronous memory. Circuit
10
is provided with a clock input signal (CLOCK) and a control signal (SLEEP), and provides differential clock signals CLK and CLKB as shown in FIG.
1
. Circuit
10
includes an inverter
12
, N-channel transistor
16
, P-channel transistor
14
, latch
18
, and inverter
20
. Inverter
12
includes N-channel transistor
15
and P-channel transistor
13
. The CLOCK signal is provided as an input to the gates of transistors
13
and
15
. The SLEEPB control signal is active as a logic low and causes N-channel transistor
16
to be off, thus preventing current flow through transistors
13
and
15
when the SLEEPH control signal is active. Also, when SLEEPB is active, P-channel transistor
14
is on causing the output terminal of inverter
12
to be a logic high irregardless of the logic state of signal CLOCK.
Latch
18
has an input coupled to the output of inverter
12
, and an output coupled to the input of inverter
20
. Inverter
20
provides a buffered clock signal CLK, and the output of inverter
12
provides a logical complement of signal CLK labeled “CLKB”. Circuit
10
is supplied with a power supply voltage labeled “V
DD
”. The level shifting of clock signal CLOCK is done by transistors
13
,
15
, and
16
. Latch
18
is required to provide hysteresis.
Circuit
10
is designed to interface with an external circuit that operates at the same power supply voltage V
DD
. The external circuit provides clock signal CLOCK to circuit
10
as a “rail-to-rail” signal at about V
DD
. The transistors of circuit
10
all contain equal gate oxide thickness layers. The trip point of inverter
12
is determined by the relative sizes of transistors
13
and
15
. If circuit
10
was used to interface with an external circuit that provided the clock signal at a higher voltage than V
DD
, transistors
13
and
15
may need to be fabricated with a thicker gate oxide to handle the higher voltage clock signal. However, converting transistors
13
and
15
to have relatively thicker gate oxide layers does not result in a high speed clock input buffer. To satisfy the trip point requirement, transistor
13
would have to be made excessively large or the size of transistor
15
would have to be made excessively small, which would further degrade performance.
FIG. 2
illustrates another conventional input buffer circuit
30
that is currently used in the IC industry. Input buffer circuit
30
includes series-connected inverters
32
and
34
and is for buffering input signals from an IC operating at a first power supply voltage (e.g. 3.3 volts) V
DDX
and another IC operating at a second lower power supply voltage V
DD
(e.g. 1.8 volts). Each of the transistors of input buffer circuit
30
have relatively thicker gate oxide layers to handle the stress from the higher power supply voltage V
DDX
and the input signal CLOCK. Inverter
34
provides a level shifting function.
Input buffer circuits
10
and
30
both suffer from some of the same disadvantages. The thicker oxide transistors have a slower switching speed than their thin oxide counterparts. Also, the level shifter increases propagation delay. Because in synchronous integrated circuits, such as a synchronous memory, the clock marks the beginning of a cycle, the faster the clock is, the faster the memory can operate. The above conventional input buffer circuits
10
and
30
are generally inadequate for high speed operation when a level shifting function is required.
Therefore, a need exists in the industry to improve the performance and response time of clock input buffers for synchronous integrated circuits, such as synchronous memories, while simultaneously ensuring that voltage compatibility is still adequate. Such an integrated circuit is provided by the present invention, whose features and advantages will be better understood with the attached drawings in conjunction with the following detailed description.


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patent: 5300835 (1994-04-01), Assar et al.
patent: 5546355 (1996-08-01), Raatz et al.
patent: 5818258 (1998-10-01), Choi
patent: 5926055 (1999-07-01), Kashmiri et al.
patent: 6043699 (2000-03-01), Shimizu
patent: 6054875 (2000-04-01), Wayner
patent: 6094083 (2000-07-01), Noda
patent: 6097214 (2000-08-01), Troussel et al.

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