Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-06-29
2002-05-07
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230020
Reexamination Certificate
active
06385123
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the integrated technology field and relates, more specifically, to an integrated circuit having a decoder unit.
Decoder units serve for decoding input signals, as a function of which they activate their outputs. Decoder units are used for example in the form of address decoders in integrated memories. Many of the memories have a column decoder for decoding column addresses and a row decoder for decoding row addresses. Memory cells that are to be selected are situated at crossover points between the rows and the columns. SGRAMs (Synchronous Graphic Random Access Memories) are a special type of integrated memories. They have a block writing operating mode, in which a plurality of columns are accessed simultaneously during a write access, whereas in a normal operating mode or during read accesses, in principle only one column is accessed simultaneously. For this purpose, the column decoder of an SGRAM has an additional input via which the number of outputs of the column decoder that are to be activated simultaneously can be controlled.
Due to the provision of the further input signal fed in via the additional input in the case of the column decoder of the SGRAM, the latter has to be provided with additional logic gates in the column decoder compared with memories which do not have a block writing operating mode. As a result, the implementation of the column decoder becomes more complicated and the input signals fed in via its inputs have to be passed via a greater number of logic gates. This means that a column decoder of this type operates more slowly than column decoders which do not enable a block writing operating mode. For this reason, the addressing of the columns in SGRAMs of this type during write accesses and read accesses, both in the block writing operating mode and in the normal operating mode, takes place more slowly than in memories which do not have a block writing operating mode.
SUMMARY OF THE INVENTION
The object of the invention is to provide an integrated circuit having a decoder unit which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and in which in each case different decoding is effected in different operating modes, where the decoding speed can be optimized for each operating mode.
With the above and other objects in view there is provided, in accordance with the invention, an integrated circuit, comprising:
a first decoder unit having a number
1
inputs for receiving input signals to be decoded and a number n outputs to be activated in dependence on the input signals;
a second decoder unit connected in parallel with the first decoder unit, the second decoder unit having
1
inputs for receiving the input signals to be decoded differently from the first decoder unit and n outputs to be activated in dependence on the input signals;
the inputs of the second decoder unit being connected to a respective one of the inputs of the first decoder unit;
n lines to be selected and each connected to a respective one of the outputs of the first and second decoder units;
in a first operating mode, the first decoder unit determining, via the outputs thereof, a potential of the lines to be selected, and, in a second operating mode, the second decoder unit determining, via the outputs thereof, the potentials of the lines to be selected.
In other words, the integrated circuit has a first decoder unit and a second decoder unit connected in parallel with the latter. The decoder units decode the input signals fed to them in a different way in each case. The inputs of the second decoder unit are connected to a respective one of the inputs of the first decoder unit. The integrated circuit has lines to be selected, which are each connected to a respective one of the outputs of the two decoder units. Via their outputs, the first decoder unit and the second decoder unit determine, in a first operating mode and in a second operating mode, respectively, the potentials of the lines to be selected.
In the two operating modes, the two decoder units enable in each case different activation of the lines to be selected, as a function of the input signals. In contrast to circuits in which there is merely a decoder unit which performs in each case different decodings in two operating modes, the two decoder units of the integrated circuit according to the invention can be optimized with regard to the respective decoding that they are to perform.
In accordance with an added feature of the invention, the integrated circuit is a memory with a plurality of memory cells arranged at crossover points of word lines and bit lines. The input signals thereby are address signals for selectively addressing the word lines and the bit lines.
By way of example, the integrated circuit may be an integrated memory of the SGPAM type, in which the two decoder units each serve for decoding a column address formed by the input signals. The first operating mode may then be a block writing operating mode, for example, in which the first decoder unit, for each column address fed to it, activates in each case a plurality of the lines to be selected, and the second operating mode may be a normal operating mode in which, during write and read accesses, the second decoder unit, for each column address fed to it, activates only in each case one of the lines to be selected.
In accordance with an additional feature of the invention, the first operating mode defines a write access to the memory cells and the second operating mode defines a read access to the memory cells.
In accordance with another feature of the invention, the first decoder unit has at least one additional input for feeding in a further input signal for additionally influencing an activation of the outputs of the first decoder unit.
In accordance with a further feature of the invention, the further input signal received via the additional input of the first decoder unit determines a number of the outputs to be activated in each case simultaneously by the first decoder unit.
In accordance with again an added feature of the invention, a multiplexer is connected between the outputs of the first and second decoder units and the lines to be selected, the multiplexer conductively connecting the outputs of the first decoder unit to the lines to be selected in the first operating mode, and conductively connecting the outputs of the second decoder unit to the lines to be selected in the second operating mode.
As an alternative to this, the outputs of the two decoder units may also be connected directly to the lines to be selected, in each case the outputs of one of the two decoding units being activated in each operating mode, with the result that the associated decoder unit does not influence the potentials on the lines to be selected.
In accordance with a concomitant feature of the invention, the first and second decoder units are alternatively operable decoder stages of a multistage decoder circuit, and the decoder circuit having at least one further decoder stage with n inputs each connected to a respective one of the lines to be selected.
This development has the advantage that the two decoder units merely form a subcircuit of the decoder circuit, with the result that a portion of the decoding of the input signals is effected via the further decoder stage in both operating modes. Since the further decoder stage is utilized in both operating modes, the decoder circuit can be produced with a relatively small area.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having a decoder unit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of
Dietrich Stefan
Schöniger Sabine
Schrögmeier Peter
Weis Christian
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nelms David
Stemer Werner H.
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