Integrated circuit and associated fabrication process

Details Integrated circuit and associated fabrication process Integrated circuit and associated fabrication process

1999-11-24

2002-05-21

Quach, Tuan (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S773000, C257S774000

Reexamination Certificate

active

06392299

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits, and, more particularly, to an integrated circuit comprising a stack of conducting layers separated by insulating layers, and to a fabrication process thereof.
BACKGROUND OF THE INVENTION
In an integrated circuit that includes conducting layers separated by one or more insulating layers, it is necessary to establish electrical connections between various levels of the conducting layers. Typically, two conducting layers are electrically connected by holes provided in the insulating layer and filled with metal, with such a connection being called a via.
The integrated circuits may be produced in a conventional manner by depositing and then etching a metal layer, and by filling the spaces exposed by the etching with a dielectric material. The integrated circuits may also be produced using a process called damascene, in which a first insulating layer is deposited on a metal layer of level n−1. The holes through this insulating layer are etched, the metal forming the via is deposited and polished to be level with the upper surface of the insulating layer. Then a new insulating layer is deposited on the via of level n thus formed. The trenches forming the future lines are etched, and the. metal forming the lines of the metal layer of level n is deposited. The metal is polished to be level with the upper surface of the insulating layer, etc. This process is well suited to the production of lines and vias made of copper since this material can not be etched at room temperature and has advantageous electrical characteristics for lines having a small cross section. This process can also be used with metals normally forming the lines and vias.
In a double damascene process, the metal is deposited both in the vias and the lines, and then polished. In one method of implementation, a stop layer, usually made of a nitride, is provided between an insulating layer of the vias and the lines. To obtain the final structure, there needs to be excellent selectivity of the etching of the oxide forming the insulating layer as compared with the nitride.
To increase the density of an integrated circuit, attempts have been made to reduce the width of the metal lines and the width of the dielectric materials separating two metal lines. However, the electrical capacitance existing between two adjacent metal lines is inversely proportional to the distance separating them. By reducing this distance to increase the density of the circuit, the interline capacitance is increased. This is a problem since it results in an increase in the propagation constant &tgr; of the electrical signal in the lines:
&tgr;=R*C
The variable R is the resistance of the metal line, and C is the interline capacitance. The stray coupling between two electrical signals propagating in two adjacent lines, i.e., crosstalk, is also increased. his interline capacitance is proportional to the permitivity coefficient k of the dielectric material used, and is proportional to the lateral area of the lines. The tendency is to use dielectric materials having a low permitivity coefficient k, or to use less resistive conducting materials, such as copper, to reduce the height of the lines and the lateral area.
However, the use of dielectric materials having a low permitivity coefficient and the use of less resistive conducting materials still cause integration problems in the field of integrated-circuit fabrication.
SUMMARY OF THE INVENTION
An object of the present invention is to remedy the drawbacks of the abovementioned techniques by providing an integrated circuit having reduced interline capacitances.
The integrated circuit comprises tracks of at least one metal level provided with dielectric layers and with metal vias connecting tracks of two adjacent levels. At least one part of at least one metal level n is split into two partial levels offset heightwise. The circuit comprises at least one via connecting a track of the upper partial level with an element lying below the dielectric layer of level n. This via passes through the dielectric layer of level n and the dielectric material separating the tracks of the lower partial level. The circuit comprises at least one via connecting a track of the lower partial level with a track of a metal level n+1. This via passes through the dielectric layer of level n+1 and the dielectric material separating the tracks of the upper partial level. The average distance mutually separating the conducting tracks are increased and the interline capacitances which are inversely proportional to this distance are decreased.
In one embodiment, part of the tracks of the metal level are divided between an upper partial level and a lower partial level.
In another embodiment, part of the tracks of the metal level are provided without them intersecting.
In yet another embodiment, the upper and lower partial levels are adjacent.
In a further embodiment, the upper and lower partial levels are separated by an additional layer of dielectric material.
In another embodiment of the invention, at least one via connecting a track of the upper partial level with an element lying below the dielectric layer of level n pass through an additional layer of dielectric material. At least one via connecting a track of the lower partial level with a track of a metal level n+1 pass through the additional layer of dielectric material. The upper and lower partial levels may be separated by an additional layer of dielectric material and by a stop layer.
In the process for fabricating an integrated circuit according to the invention, a second dielectric layer is deposited on a first dielectric layer provided with vias. Trenches are etched in the second dielectric layer and conducting tracks are produced by filling the trenches with a metal. A third dielectric layer is deposited. Trenches are etched in the third dielectric layer and conducting tracks are produced by filling the trenches with metal. At least one part of the metal level thus obtained is split into two partial levels offset heightwise.
In one embodiment, a stop layer may be deposited before the third dielectric layer to control the depth of the trenches.
In the process for fabricating an integrated circuit according to the invention, a stop layer is deposited on a first dielectric layer and holes are etched in the stop layer. A second dielectric layer is deposited. Trenches are etched in the second dielectric layer, and holes are etched in the first dielectric layer at positions corresponding to the holes in the stop layer. Vias and conducting tracks are produced by filling the holes and the trenches with metal. A third dielectric layer and a second stop layer are deposited, and holes are etched in the second stop layer. A fourth dielectric layer is deposited. Trenches are etched in the fourth dielectric layer, and holes are etched in the third dielectric layer at the positions corresponding to the holes in the second stop layer. Vias and conducting tracks are produced by filling the holes and the trenches with metal to obtain at least one part of the metal level that is split into two partial levels offset heightwise.
In the process for fabricating a first metal layer is deposited on a dielectric layer provided with vias, and then etched. The open spaces left by the etching are filled with dielectric material. A second metal layer is deposited and then etched. The open spaces left by the etching are filled with dielectric material to obtain at least one part of the metal level that is split into two partial levels offset heightwise.
The masks used for the fabrication of the conducting lines may include recessed zones corresponding to extensions used for respectively connecting a line of a given upper or lower partial level with a via located opposite the partial level, under the lower partial level or on the upper partial level. Thus, an integrated circuit is provided which can be produced with very small widths of dielectric material between lines because of the

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