Patent
1997-04-09
1999-03-16
Barry, Esq., Lance Leonard
G06F 1300
Patent
active
058840680
ABSTRACT:
A microprocessor that operates at the speed of the the bus or at a speed which is a multiple of the bus speed-on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals for operations within the microprocessor and bus clock signals for data transfer operations on the bus. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses.
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Beutler Robert R.
Conary James W.
Barry, Esq. Lance Leonard
Intel Corporation
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