Integrated circuit furnishing a segmented input circuit

Details Integrated circuit furnishing a segmented input circuit Integrated circuit furnishing a segmented input circuit

1990-06-11

1991-04-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307303, 3074651, 307475, 3072963, H03K 1708, H03K 1716, H03K 19003, H03K 19092

Patent

active

050102605

ABSTRACT:
An input circuit for an integrated circuit furnishes a level shifting buffer portion adjacent a respective bond pad carried at the margin of the substrate while furnishing a clocked or latched portion adjacent the internal circuit of the integrated circuit. A lead extending from the level shifting or buffer portion to the clocked or latched portion carries the external signal applied to the bond pad and level shifted by the level shifting or buffer portion. The lead is subject to the parasitic resistance and capacitance of the integrated circuit. A multiplexer can be used to select among the level shifting portions for applying a single signal to the clocked portion and the clocked or latched portion can be part of a larger latch that receives plural signals for transmission to the internal circuit at appropriate times.

REFERENCES:
patent: 4523106 (1985-06-01), Tanizawa et al.
patent: 4600995 (1986-07-01), Kinoshita
patent: 4607339 (1986-08-01), Davis
patent: 4689654 (1987-08-01), Brockmann
patent: 4710842 (1987-12-01), Suzuki et al.
patent: 4761566 (1988-08-01), Inoue et al.
patent: 4763022 (1988-08-01), Sheldon

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