Integrated circuit for sampling a sequence of data packets...

Details Integrated circuit for sampling a sequence of data packets... Integrated circuit for sampling a sequence of data packets...

2007-09-12

2009-08-11

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S230010, C365S189170, C365S193000, C365S230030, C365S230040

Reexamination Certificate

active

07573760

ABSTRACT:
An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.

REFERENCES:
patent: 6259627 (2001-07-01), Wong
patent: 6522596 (2003-02-01), Gillingham et al.
patent: 2004/0057331 (2004-03-01), Graaff
patent: 2004/0222828 (2004-11-01), Ishikawa

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