Integrated circuit for handling buffer contention and method the

Details Integrated circuit for handling buffer contention and method the Integrated circuit for handling buffer contention and method the

1998-07-13

2000-11-14

Tokar, Michael

Electronic digital logic circuitry

Tri-state

326 83, 326 86, H03K 190185

Patent

active

061475106

ABSTRACT:
In one embodiment, an integrated circuit (10, 110) has a contention detection circuit (12, 112) coupled to a tri-stateable output buffer (18, 118). The contention detection circuit (12, 112) provides a contention tri-state control signal (34, 134) to the tri-stateable output buffer (18, 118) in order to place it in a tri-stated condition when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110). Thus, external and/or internal buffer contention is avoided when an external device (31, 131), such as a computer, supplies power to an input/output pad (22, 122) on the integrated circuit (10, 110).

REFERENCES:
patent: 5767701 (1998-06-01), Choy et al.
patent: 5880603 (1999-03-01), Shigehara et al.
patent: 6020757 (2000-02-01), Jenkins, IV
U.S. Patent Serial No. 08/942,740; Pappert, et al.; "Integrated Circuit Having Buffering Circuitry With Slew Rate Control," filed Oct. 2, 1997.

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