Electronic digital logic circuitry – Tri-state
Reexamination Certificate
2000-08-11
2002-04-30
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Tri-state
C083S086000
Reexamination Certificate
active
06380760
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to integrated circuits, and more particularly to a method and apparatus for handling integrated circuit buffer contention.
BACKGROUND OF THE INVENTION
During operation, a computer may be connected to another device such as a printer that contains a semiconductor device, such as an application specific integrated circuit (ASIC). At times, the printer may be turned off while the computer is still on. Under these conditions, the semiconductor device within the printer is powered down. If the computer drives a high level to the printer while it is powered down, an input/output buffer on the semiconductor device may be powered up by the computer. However, since the internal circuitry of the semiconductor device is powered down, this can cause external or off chip buffer contentions. The off chip contentions occur because the semiconductor device does not have a clock signal to clear out contentions that occur when the input/output pad is powered up and the core of the semiconductor device is powered down. In addition, internal or on chip buffer contentions can occur if an external source powers up an input/output buffer on a powered up semiconductor device that is supplying power to other input/output buffers on the semiconductor device. Internal and external buffer contentions can cause significant discharge current that can drain the battery on a laptop computer or similar device. Accordingly, a need exists for an integrated circuit that handles external as well as internal buffer contentions, and that is suitable for low power applications.
REFERENCES:
patent: 5576635 (1996-11-01), Partovi et al.
patent: 5764077 (1998-06-01), Andresen et al.
patent: 5767701 (1998-06-01), Choy et al.
patent: 5850159 (1998-12-01), Chow et al.
patent: 5880603 (1999-03-01), Shigehara et al.
patent: 6020757 (2000-02-01), Jenkins, IV
patent: 6147510 (2000-11-01), Pappert
Cooper Kent J.
Hill Susan C.
Le Don Phu
Motorola Inc.
Tokar Michael
LandOfFree
Integrated circuit for handling buffer contention and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit for handling buffer contention and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit for handling buffer contention and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2870127