Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-08-22
2004-05-04
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S797000, C257S798000
Reexamination Certificate
active
06730931
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor processing and more specifically to a device feature layout and a method of generating the same for improved chemical mechanical polishing.
2. Discussion of Related Art
As device dimensions continue to shrink modern integrated circuits now contain more and more levels of features. For example, modern high density circuits, which can contain literally tens of millions of transistors formed in a silicon monocrystalline substrate, require over six levels of metalization to electrically couple the transistors into functional circuits. Similarly, novel three-dimensional memory arrays such as described in copending U.S. patent application Ser. No. 09/560,626, filed Apr. 28, 2000 and entitled Three-Dimensional Memory Array and Method of Fabrication can utilize over nine levels of silicon rails or lines. As more and more levels of features are added to integrated circuits, the planarization of each level is essential to enable the uniform processing of subsequent levels of features. In the past, dummy features (i.e., electrically isolated inactive features) have been locally inserted between active features of a level in order enhance the chemical mechanical planarization of that level. Unfortunately, however, such techniques of “dummification” (i.e., adding dummy features locally between active features) do not take into consideration the size and density of the active features. Present dummification techniques are useful for providing uniform local planarization, however, they fail to provide mid-range planarity. Lack of mid-range planarity can cause photolithography exposure systems used to form photoresist mask for subsequent layers to print inaccurate images, thereby preventing the formation of additional levels of features.
Thus, what is desired is a method of sizing and locating dummy features in an integrated circuit device level to improve the mid-range planarity of a chemical mechanical polishing process.
SUMMARY OF THE INVENTION
The present invention is directed to a level of an integrated circuit. The level of the integrated circuit has a first area having a plurality of features having a first density and a second area adjacent to the first area wherin the second area has a plurality of dummy features having a density substantially similar to the first density.
In another embodiment of the present invention, a wafer has a plurality of semiconductor integrated circuits separated by a plurality of scribe lines. A plurality of dummy features are formed in the scribe lines.
In yet another embodiment of the present invention, a level of an integrated circuit comprises a core area having a first density of features and a peripheral area having a second density of features, wherein the second density is substantially similar to the first density.
Yet another embodiment of the present invention is directed to a method of generating a layout of an integrated circuit. Accordingly, a first layout of a level of active features is generated wherein, the first layout has a first area and a second area adjacent to the first area wherein the first area has a first density of active features and wherein the second area has a second density of active features. The size of the active features are increased or decreased in the second area so that the dinsity of the active features in the second area is similar to the density of the active features in the first area.
In yet another embodiment of the present invention, an integrated circuit having a plurality of levels of features is provided wherein at least one of said levels of features consists of a plurality of 25 &mgr;m
2
areas having a plurality of features therein, wherein the average density of the features in eah of the plurality of 25 &mgr;m
2
areas is substantially similar.
REFERENCES:
patent: 4489478 (1984-12-01), Sakuri
patent: 4500905 (1985-02-01), Shibata
patent: 4711701 (1987-12-01), Mclevige
patent: 4916514 (1990-04-01), Nowak
patent: 4949162 (1990-08-01), Tamaki et al.
patent: 4963501 (1990-10-01), Ryan et al.
patent: 4973562 (1990-11-01), Den Blanken
patent: 5032890 (1991-07-01), Ushiku et al.
patent: 5132237 (1992-07-01), Matthews
patent: 5278105 (1994-01-01), Eden et al.
patent: 5733798 (1998-03-01), Michael et al.
patent: 5745407 (1998-04-01), Levy et al.
patent: 5789120 (1998-08-01), Jang et al.
patent: 5885856 (1999-03-01), Gilbert et al.
patent: 5981384 (1999-11-01), Juengling
patent: 6171976 (2001-01-01), Cheng
patent: 6232231 (2001-05-01), Sithuraman et al.
patent: 6396158 (2002-05-01), Travis et al.
patent: 0073486 (1982-08-01), None
patent: 0395886 (1990-03-01), None
patent: 60-119749 (1985-06-01), None
patent: 11-251531 (1999-09-01), None
Yoichi Akasaka “Three Dimensional Integrated Circuit: Technology and Application Prospect”, Microelectronics Journal, vol. 20, Nos 1-2, 1989.
Yoichi Akasaka “Three Dimensional IC Trends”, Proceedings of the IEEE, vol. 74, No. 12, Dec. 1986.
“Exotic Memories Diverse Approaches” EDN Asia Magazine, Sep. 2001.
Cleeves James M.
Vyvoda Michael A.
Blakely , Sokoloff, Taylor & Zafman LLP
Eckert George
Matix Semiconductor
Nguyen Joseph
LandOfFree
Integrated circuit feature layout for improved chemical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit feature layout for improved chemical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit feature layout for improved chemical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3216799