Integrated circuit fabrication

Details Integrated circuit fabrication Integrated circuit fabrication

1997-09-29

2001-01-02

Duda, Kathleen (Department: 1756)

Radiation imagery chemistry: process, composition, or product th

Imaging affecting physical property of radiation sensitive...

Making electrical device

C430S311000, C430S394000, C430S396000

Utility Patent

active

06168904

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to the field of integrated circuit fabrication and particularly to lithographic techniques used in such fabrication which reduce optical proximity or truncation effects.
BACKGROUND OF THE INVENTION
The development of integrated circuit manufacturing has required developments in many technical areas. Many of these developments have focused on fabricating devices or features with smaller dimensions than previously used or on fabricating devices or features closer together than previously possible. Smaller dimensions permit the fabrication of more devices or other integrated circuit components per unit substrate area. Closer spacing of features yields similar advantages.
Integrated circuit fabrication has a plurality of steps in which a pattern is transferred from a mask to the wafer or substrate. The wafer is coated with a radiation sensitive material termed a resist which forms an overlying layer on the wafer or substrate. The pattern is transferred from the mask to the wafer by, for example, an optical imaging system and exposing the mask to radiation. Only selected portions of the mask transmit radiation and, therefore, only selected portions of the resist are exposed to radiation. When the resist is exposed to a suitable agent, the radiation changes the relative removal rates during development of the exposed and unexposed portions of the resist. After the resist has been patterned by removal of the selected portions to expose the underlying material, the now-exposed underlying material is modified by, for example, etching to remove material, or ion implanting to change the electrical characteristics of the material.
An example that demonstrates the problems that arise as features are reduced in size or are packed closer together near the limits of the imaging system will be discussed using a common component namely, field effect transistors, of integrated circuits. Field effect transistors have a gate structure which controls carrier flow through a channel located underneath the gate and extending from the source and drain regions located on opposite sides of the gate structure. The conducting portion of the gate structure is separated from the channel by a gate oxide. The conducting portion of the gate structure should completely cover the gate oxide; that is, the ends of the conducting portion of the gate structure should not expose the gate oxide. Due to the high spatial frequencies needed to accurately replicate the corners of the gate structure, rounding of the gate structure occurs because the higher spatial frequencies do not pass through a lens of finite numerical aperture (N.A.). When the gate structure becomes too small, truncation (or shortening) of the gate structure is observed. A proper compensation for this truncation effect requires that the gate structure be fabricated with a design dimension longer than the extent of the gate oxide. Consequently, more substrate area is used because features proximate the end of the gate structure must be moved away so that a minimum spacing to the proximity feature is maintained during pattern transfer to the resist.
The comment in the previous paragraph about the relationship between spatial frequencies and feature dimensions will be better understood from consideration of the following. Only those portions of the mask image that are transmitted through the lens that is positioned between the mask and the substrate will be reproduced in the resist. However, as features become smaller or more closely spaced, the spatial separation between the light in different diffraction orders comprising the image increases. Only lower diffraction orders are transmitted through the projection lens due to the finite numerical aperture of the lens. The information about the image contained in the higher orders is thus lost. The lens may be considered a low pass optical frequency filter which truncates at some frequency. In other words, only frequencies below a certain value are transmitted. The attainable resolution; that is, the smallest feature dimension or spacing that can be printed, is thus limited because the higher spatial frequencies are lost.
A typical lithographic process uses only a single exposure of the resist to radiation, however, double exposures have been used. See, for example U.S. Pat. No. 4,788,117, issued on Nov. 29, 1988 to Cuthbert et al. In this example, double exposures were used to provide a non-destructive means of generating a cross section of a photoresist feature to facilitate the examination of the feature.
SUMMARY OF THE INVENTION
This invention relates to a method of integrated circuit fabrication which has at least one photolithographic process step involving pattern decomposition where a mask pattern is decomposed into at least two component parts. Lithographic processing using less complex component patterns leads to a reduction of truncation and proximity effects in the final desired pattern. This pattern decomposition technique can be used either with positive or negative resists. A two-step double exposure technique allows the desired final pattern to be reproduced with sharper corners or better line size control than the conventional single exposure approach. This technique can be extended to include multi-step exposures with two or more reticle patterns. In a preferred embodiment, the subsequent exposures are performed without prior processing of the resist. Closely spaced or narrow features can be produced with improved image fidelities using this technique.


REFERENCES:
patent: 5604059 (1997-02-01), Imura

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