Integrated circuit etching

Details Integrated circuit etching Integrated circuit etching

1995-04-28

1997-03-04

Breneman, R. Bruce

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566511, 1566521, 1566531, 437228, H01L 2130

Patent

active

056075430

ABSTRACT:
A process for removing both the silicon nitride layer and polysilicon layer in a poly-buffered LOCOS process which utilizes hot phosphoric acid and nitric acid is disclosed.

REFERENCES:
patent: 3715249 (1973-02-01), Panousis
patent: 5002898 (1991-03-01), Fritzinger et al.
patent: 5215930 (1993-06-01), Lee et al.
patent: 5310457 (1994-05-01), Ziger
patent: 5437765 (1995-08-01), Loewenstein
"Silicon Processing For The VLSI Era-vol. 2-Process Integration"; Wolf; Lattice Press, Sunset Beach, Ca.; .COPYRGT.1990; pp. 17-32.
A New Deglase Process for Doped Polysilicon Larry, Lowell, Polaroid Corporation, Microelectronics Laboratory, Cambridge, Massachusetts. Apr. 1991, Solid State Technology, pp. 149-153.
Thin Film Processes, John L. Vossen and Werner Kern, RCA Laboratories, David Sarnoff Research Center, Princeton, New Jersey.
Characterization of Poly-Buffered LOCOS in Manufacturing Environment, R. L. Guldi, B. McKee, G. M. Damminga, C. Y. Yong and M. A. Beals, Texas Instruments Incorporated, Logic Operations, Semiconductor Group, Dallas, Texas.
J. Electrochem 1967, p. 423.

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