Integrated circuit dual-port memory device having reduced capaci

Details Integrated circuit dual-port memory device having reduced capaci Integrated circuit dual-port memory device having reduced capaci

1991-07-17

1994-02-15

Sikes, William L.

Static information storage and retrieval

Addressing

Multiple port access

365190, 365202, 365206, 365221, 36523003, 365231, G11C 700

Patent

active

052873226

ABSTRACT:
A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray capacitance and cross-coupling capacitance between bit lines for the two different ports. A bit line layout plan which minimizes such capacitances causes the data for one of the ports to be inverted in one-half of the array. When data from this half of the array is read or written by such port, the data being read or written must be inverted.

REFERENCES:
patent: 4870619 (1989-09-01), Van Ness
patent: 4916661 (1990-04-01), Nawaki et al.
patent: 4922459 (1990-05-01), Hidaka
patent: 4958325 (1990-09-01), Nakagome et al.
patent: 4982368 (1991-01-01), Arimoto
patent: 5012447 (1991-04-01), Matsuda et al.
patent: 5144583 (1992-09-01), Oowaki et al.

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