Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
1999-10-28
2001-02-06
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C257S618000, C257S778000
Reexamination Certificate
active
06184570
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to microelectronic devices and related fabrication methods, and more particularly to packaging of microelectronic devices and related fabrication methods.
BACKGROUND OF THE INVENTION
Integrated circuits are widely used in consumer and commercial applications. As is well known to those having skill in the art, an integrated circuit generally includes an integrated circuit die such as a silicon semiconductor die, having first and second opposing faces. Microelectronic devices such as transistors are formed in the integrated circuit die adjacent the first face. A plurality of spaced apart bonding regions such as pads also are formed on the first face to allow electrical connection of the microelectronic devices to external of the integrated circuit die.
As the integration density of integrated circuit devices continues to increase, increasing demands may be placed on the packaging thereof. In particular, it may be desirable to provide large numbers of input/output connections for the integrated circuit device in order to provide power, control, signal, data, and other connections. Moreover, as the integration density continues to increase, the thermal management of the integrated circuit may become increasingly difficult, in order to dissipate the heat that is generated during the operation of the integrated circuit.
In order to accommodate these high performance input/output connection and thermal management needs, a variety of packages have been developed for packaging integrated circuit dies. In order to provide large numbers of input/output connections, many of these packages use solder bumps to connect the bonding regions to a mounting substrate, also referred to as a second level package. Examples of packaging technologies using solder bumps include “flip chip” technology, also referred to as Controlled Collapsed Chip Connection (C-4). Another packaging technology that uses solder bumps is referred to as Ball Grid Array (BGA) technology. These technologies are well known to those having skill in the art and need not be described further herein.
A major problem in microelectronic packaging using solder bumps is the reliability problems that may be introduced due to thermal cycling of the integrated circuit die. In particular, since the integrated circuit die generally has a different co-efficient of thermal expansion than the mounting substrate, stresses may be placed on the bonding regions and/or on the solder bumps that mechanically connect the bonding regions of the integrated circuit die with the mounting substrate, during thermal cycling of the integrated circuit die. These thermal stresses may eventually fatigue the solder bump and/or the connection with the bonding regions and/or the mounting substrate, which can lead to early failure of the microelectronic package.
Many attempts have been made to reduce the thermal stress on solder bumps and/or bonding regions due to thermal cycling. For example, U.S. Pat. No. 5,598,036 to Ho entitled Ball Grid Array Having Reduced Mechanical Stress describes the use of two sets of solder joints that have different melting points to thereby minimize the level of internal mechanical stress. U.S. Pat. NO. 5,690,270 to Gore entitled Surface Mounting Stress Relief Device and Method describes a pin that is coupled to an integrated circuit and that loosely fits within a feedthrough in a printed circuit board so that movement caused by a coefficient of thermal expansion mismatch between materials of the pin and printed circuit board is absorbed by movement of the pin within the feedthrough. U.S. Pat. No. 5,744,975 to Notohardjono, et al. entitled Enhanced Defect Elimination Process for Electronic Assemblies via Application of Sequentially Combined Multiple Stress Processes describes a method for combining three sequential test steps into a single stress test in order to screen microelectronic packages. Finally, U.S. Pat. No. 5,804,771 to McMahon et al. entitled Organic Substrate (PCB) Slip Plan “Stress Deflector” for Flip Chip Devices describes a layer on a substrate that allows an integrated circuit to float and expand at a different rate than the substrate when the package is thermally cycled.
Unfortunately, these and other stress reduction systems and methods may complicate the manufacture and/or increase the cost of the integrated circuit die and/or the microelectronic package. Accordingly, there continues to be a desire for stress reduction techniques that need not unduly complicate the manufacture of the integrated circuit die and/or the microelectronic package and need not unduly increase the cost thereof.
SUMMARY OF THE INVENTION
It therefore is an object of the present invention to provide improved integrated circuit dies, microelectronic packages and fabrication methods thereof.
It is another object of the present invention to provide improved thermal stress reducing structures and methods for integrated circuit dies and microelectronic packages.
It is still another object of the present invention to provide thermal stress reducing structures and methods for integrated circuit dies and microelectronic packages that need not unduly increase the cost and/or complexity and/or fabrication complexity of the integrated circuit dies and/or microelectronic packages.
These and other objects may be provided according to the present invention by an integrated circuit that includes an integrated circuit die having first and second opposing faces, a plurality of spaced apart bonding regions on the first face, and at least one groove in the second face. The at least one groove allows the die to flex upon application of stress to the bonding regions due to thermal cycling of the integrated circuit die, compared to absence of the at least one groove. Preferably, a plurality of grooves are provided, a respective one of which extends between a respective pair of adjacent spaced apart bonding regions. In one embodiment, the integrated circuit die may be about 0.6 mm thick and the grooves may be about 0.5 mm deep.
As is well known to those having skill in the art, the faces of an integrated circuit die generally include a central portion and a peripheral portion. In a peripheral ball grid array device, the plurality of spaced apart bonding regions extend along the peripheral portion but may not extend into the central portion. According to the invention, a respective groove preferably extends from an end of the first face across the peripheral portion. In contrast, in a flip chip device, wherein the spaced apart bonding regions are located in the peripheral portion and in the central portion, a respective groove preferably extends across the first face, including across the peripheral portion and across the central portion.
In order to enhance thermal conduction from the integrated circuit die, a thermally conductive material may be placed in the groove and/or on the second face. Other conventional thermal conduction techniques may be used to conduct heat from the second face. In fact, by providing greater surface area, the grooves may improve the thermal conduction from the die in an air, liquid, or other fluid-cooled environment.
Integrated circuit dies according to the present invention may be packaged by providing a plurality of solder bumps, a respective one of which is mechanically attached to a respective bonding region. A mounting substrate is mechanically attached to the plurality of solder bumps, opposite the bonding regions. A thermal conduction structure also may be thermally connected to the second face to conduct heat away from the second face.
The grooves may be fabricated, according to the invention, by sawing and/or etching the grooves in the second face. The sawing and/or etching may be performed at the wafer stage, before the integrated circuit dies are singulated. Alternatively, the sawing and/or etching may take place after the integrated circuit dies are singulated from the wafer.
By forming at least one groove in the second face of an integrated circuit die, the die can flex upon a
Gupta Rahul
MacDonald, Jr. James D.
Clark Sheila V.
Ericsson Inc.
Myers Bigel & Sibley & Sajovec
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