Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1999-12-30
2003-08-12
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S786000, C257S723000
Reexamination Certificate
active
06605875
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and, in particular, to the packaging of integrated circuits.
BACKGROUND OF THE INVENTION
Electronic devices such as cellular telephones and notebook computers typically contain a number of integrated circuit (IC) packages mounted to a printed circuit board (PCB). IC packages typically include a single IC die (or chip) on a substrate or leadframe. The die and substrate are encapsulated in a material such as plastic. The encapsulated packages are then mounted to another substrate such as a PCB.
Multichip modules (MCM) are IC packages that can contain two or more integrated circuits. The size of the electronic device that uses MCMs can be reduced because MCMs typically have a number of individual IC dice mounted within a single package in a laterally adjacent manner. The outer dimensions of all the individual elements limit the minimum footprint of a multichip module, however. Moreover, multichip module substrates are typically constructed from ceramic, silicon, metal or printed circuit board materials that are relatively expensive to produce. Considerable effort has been expended to provide an electronic package that has a minimal footprint and volume and that can be assembled with conventional plastic injection molding techniques without adding expensive interconnecting substrate components.
FIG. 1
shows another type of IC package configuration that attempts to decrease the footprint and volume of the IC package. This type of IC package is known as a Stacked Chip Scale Package (SCSP). IC package
100
includes stacked IC dice. The SCSPs
101
are formed by stacking several sets of IC dice on a long substrate, wire bonding, encapsulating the IC dice, and then slicing the substrate and encapsulant to separate each SCSP
101
.
Substrate
110
includes bond fingers
112
connected to conductive traces
114
on the top surface of the substrate
110
. Bond fingers
112
are conductive areas on the substrate
110
that provide locations for wire bonding of the IC dice to the substrate
110
. Vias
116
are conductive interconnects that extend through the substrate
110
to electrically connect traces
114
to conductive pads
117
on the bottom surface of the substrate
110
. One example of a substrate is a printed circuit board (PCP). Other examples of materials for substrate
110
are: FR4, BT, tape automated bonding (TAB) tape material, ceramic, silicon on sapphire (SOS), or a multi-layered substrate such as OLGA.
The SCSP
101
shown in
FIG. 1
is connected to a circuit board (not shown) by solder balls
118
, which are placed on pads
117
on the bottom surface of the substrate
110
. Other types of IC packages may include leads that extend laterally with respect to the dice within the package for connection to an external circuit board.
FIG. 1
also shows a first die
120
mounted to substrate
110
. Second die
130
is mounted on the top surface of first die
120
. An adhesive
103
such as epoxy is used to mount the die. After first die
120
and second die
130
are mounted, they are wire bonded to the substrate
110
. First die
120
has bond pads
122
on its top surface near its edges, and second die
130
has bond pads
132
on its top surface near its edges. Bond wires
124
connect bond pads
122
of first die
120
to the substrate
110
, while bond wires
134
connect bond pads
132
of second die
130
to the substrate
110
.
FIG. 2
shows a top view of IC package
100
after wire bonding and before encapsulation. First die
120
is mounted to substrate
110
. Bond pads
122
are connected by bond wires
124
to bond fingers
112
. Second die
130
is mounted on top of first die
130
. Bond pads
132
on second die
130
are connected to bond fingers
112
by bond wires
134
. The area in the center of first die
120
limits the size of second die
130
because second die
130
cannot cover bond pads
122
of first die
120
. This is especially problematic in dice having bond pads adjacent all four edges.
FIG. 3A
shows an IC die configuration
200
that includes a first die
220
and a second die
230
stacked on top of first die
220
. First and second dice
220
and
230
are stacked on substrate
210
. Substrate
210
has bond fingers
212
adjacent two opposite ends, as shown in FIG.
2
. Bond fingers
212
correspond to bond pads on first and second dice.
First die
220
has bond pads
222
adjacent two opposite edges rather than adjacent all four edges as in the first die
120
of FIG.
2
. In order for second die
230
to be stacked on top of first die
220
, second die
230
must fit between bond pads
222
of first die
220
. Thus, the size of second die
230
is limited by the bond pad configuration on the first die
220
.
FIG. 3B
shows an IC die configuration
200
′ that includes a first die
220
′ and a second die
230
′ stacked on top of first die
220
′. First and second dice
220
′ and
230
′ are rectangular and have bond pads
222
′ and
232
′, respectively, near opposing short edges. Die configuration
200
′ allows two dice that are the same size to be stacked and yet leave the bond pads of the lower die exposed, but these rectangular dice must be stacked with their respective axes perpendicular. Also, the second die
230
′ must be narrow enough to fit between the bond pads
222
′ of the first die
220
′. The size of the second die
230
′ is therefore limited.
SUMMARY OF THE INVENTION
In one embodiment, an apparatus includes a lower die having a top surface and two adjacent keep out areas on the top surface. The keep out areas are next to two adjacent edges of the lower die. The lower die further includes at least one non-bonding edge area. An upper die is stacked on the lower die such that the two adjacent keep out areas are exposed to accept wire bonds.
REFERENCES:
patent: 5177669 (1993-01-01), Juskey et al.
patent: 5216283 (1993-06-01), Lin
patent: 5229960 (1993-07-01), De Givry
patent: 5239447 (1993-08-01), Cotues et al.
patent: 5366933 (1994-11-01), Golwalkar et al.
patent: 5373189 (1994-12-01), Massit et al.
patent: 5422435 (1995-06-01), Takiar et al.
patent: 5614766 (1997-03-01), Takasu et al.
patent: 5633530 (1997-05-01), Hsu
patent: 5777345 (1998-07-01), Loder et al.
patent: 5780925 (1998-07-01), Cipolla et al.
patent: 5973403 (1999-10-01), Wark
patent: 5998864 (1999-12-01), Khandros et al.
patent: 6133637 (2000-10-01), Hikita et al.
patent: 0 782 191 (1997-07-01), None
patent: 3-165550 (1991-07-01), None
patent: 4-99056 (1992-03-01), None
Blakely , Sokoloff, Taylor & Zafman LLP
Cruz Lourdes
Cuneo Kamand
Intel Corporation
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