Integrated circuit devices using fuse elements to generate...

Details Integrated circuit devices using fuse elements to generate... Integrated circuit devices using fuse elements to generate...

1999-05-20

2001-03-13

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

C327S526000

Reexamination Certificate

active

06201432

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 98-19869, filed May 29, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to the field of integrated circuit devices, and, more particularly, to fuse programmable integrated circuit devices.
BACKGROUND OF THE INVENTION
In some integrated circuit memory devices, different operating modes can be selected on the semiconductor chip before packaging. For example, a memory device may be capable of operating in various modes, such as page mode, nibble mode, burst mode, and static mode. In such a memory device, the desired operation mode may be chosen by cutting a predetermined fuse or set of fuses. In addition, fuses can be used to select among other options relating to, for example, propagation delay adjustment, pulse width adjustment, transistor width adjustment, and current level adjustment. Fuses can also be used to repair memory devices, including defective memory cells. Thus, broadly stated, a semiconductor device can be programmed to exhibit a certain set of characteristics or features by selectively cutting or leaving intact various fuse elements. To determine the status of a particular fuse, a fuse signature circuit can be used to determine if the fuse element is cut or intact.
The aforementioned applications for fuses are described, for example, in U.S. Pat. No. 4,446,534 entitled “PROGRAMMABLE FUSE CIRCUIT,” U.S. Pat. No. 4,730,129 entitled “INTEGRATED CIRCUIT HAVING FUSE CIRCUIT,” U.S. Pat. No. 4,773,046 entitled “SEMICONDUCTOR DEVICE HAVING FUSE CIRCUIT AND DETECTING CIRCUIT FOR DETECTING STATES OF FUSES IN THE FUSE CIRCUIT,” U.S. Pat. No. 5,428,311 entitled “FUSE CIRCUITRY TO CONTROL THE PROPAGATION DELAY OF AN IC,” U.S. Pat. No. 5,491,444 entitled “FUSE CIRCUIT WITH FEEDBACK DISCONNECT,” U.S. Pat. No. 5,701,274 entitled “SEMICONDUCTOR DEVICE WITH SELECTABLE DEVICE INFORMATION,” U.S. Pat. No. 5,726,585 entitled “SWITCHING CIRCUIT FOR USE INA SEMICONDUCTOR MEMORYDEVICE,” U.S. Pat. No. 5,767,732 entitled “CIRCUIT FOR PERMANENTLY ADJUSTING A CIRCUIT ELEMENT VALUE IN A SEMICONDUCTOR INTEGRATED CIRCUIT USING FUSE ELEMENTS,” and U.S. Pat. No. 5,818,285 entitled “FUSE SIGNATURE CIRCUITS FOR MICROELECTRONIC DEVICES.”
In addition to these applications, fuse elements or fuse circuits have also been used to perform selection functions. With reference to
FIG. 1
, a conventional semiconductor device
10
is shown to comprise a selection circuit
15
and an internal circuit
20
. The selection circuit
15
typically has at least one fuse element (not shown), and controls the operation of the internal circuit
20
in accordance with a fuse cutting operation.
A circuit diagram of the selection circuit
15
according to the prior art is shown in FIG.
2
. The selection circuit
15
includes a master fuse MF, which is electrically connected between a power supply voltage VCC and an output terminal ND
1
, and a resistor R
1
, which is electrically connected between the output terminal ND
1
and a ground or common voltage VSS. The master fuse MF typically comprises a laser fuse. Before the master fuse MF is cut, the output terminal ND
1
is driven to a logically high level (hereinafter logic one level) that is approximately equal to the power supply voltage VCC, which thereby activates the internal circuit
20
. Conversely, after the master fuse MF is cut, the output terminal ND
1
is pulled down to a logically low level (hereinafter logic zero level) that is approximately equal to the ground or common voltage VSS, which thereby deactivates the internal circuit
20
.
If the master fuse MF is cut imperfectly, however, the operation of the internal circuit
20
and ultimately the semiconductor device
10
may not be reliably predicted. For example, after the master fuse MF is cut, remnants of the master fuse MF may act as a resistor. This may cause the voltage level at the output terminal NDI to fall between the standard logic one and logic zero voltage levels, which can cause the behavior of the internal circuit
20
to be indeterminate.
Consequently, there exists a need for improved integrated circuit devices that can be reliably programmed through the use of fuses.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved fuse programmable integrated circuit devices.
It is another object of the present invention to provide fuse programmable integrated circuit devices that can generate selection signals for controlling other circuits or devices with reduced susceptibility to fuse remnant defects.
These and other objects, advantages, and features of the present invention are provided by integrated circuit devices that include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative.
Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e., one or more fuses have been cut) typically do not affect the output signal.
In accordance with an aspect of the invention, the fuse programmable input circuit may include a pair of voltage divider circuits that generate the first and second differential input signals. In accordance with another aspect of the invention, the comparator circuit may include a differential amplifier circuit.
Integrated circuit decoding devices according to the present invention include a redundant address generator that is operatively connected to a selection circuit. The redundant address generator includes a plurality of fuses that can be selectively cut to prevent signals from passing therethrough to reach an output terminal.
In accordance with an aspect of the invention, the selection circuit generates a control signal through a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates the control signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative.
Thus, the redundant address generator, which can implement a decoding function through selective cutting of the appropriate fuses, can be activated or deactivated via the control signal from the selection circuit. Moreover, the control signal can be reliably controlled through the fuse programmable input circuit. In particular, the control signal is typically unaffected by fuse remnants that may remain after the fuse programmable input circuit is programmed.


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