Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-01-17
2003-11-25
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S238000, C438S253000, C438S396000
Reexamination Certificate
active
06653155
ABSTRACT:
RELATED APPLICATION
This application claims priority from Korean Application No. 2001-15717, filed Mar. 26, 2001, the disclosure of which is hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit devices and methods for manufacturing the same.
Various integrated circuit devices, including semiconductor memory devices such as DRAMs, include a resistor pattern. For example, a resistor pattern may be provided having a resistance chosen to control a signal transmission characteristic of the integrated circuit device. The resistor pattern may be formed, for example, using a polysilicon layer having a specific resistance of thousands of microohms (&mgr;&OHgr;) per centimeter (cm) (&mgr;&OHgr;·cm).
The resistor pattern for a semiconductor memory device, such as a DRAM, may be formed in a circuit including a capacitor. The resistor pattern may be formed by patterning an upper capacitor electrode material layer and a doped polysilicon layer, which are sequentially stacked on a substrate of the device, using a single mask before a metal conductive line is formed. Such an approach may be used as it is generally relatively easy to control a thickness of the polysilicon layer to control the resistance value of the resistor pattern. Furthermore, the resistor pattern is typically formed after a high temperature heating process that also may affect the resistance value of the resistor pattern.
However, a problem may arise where the upper capacitor electrode is a low resistance material, such as a material having a specific resistance of several &mgr;&OHgr;·cm up to hundreds of &mgr;&OHgr;·cm. Examples of such materials include ruthenium (Ru), platinum (Pt), and the like. Where such a material is present, its low resistivity characteristics may limit the ability to provide a desired resistance value for the resistor pattern. To form a resistor pattern having a desired resistance value, the resistor pattern may have to be formed with a relatively thin thickness or with a relatively long length to provide a desired resistance given the low specific resistance of the material. Therefore, it is generally not possible to simultaneously form such an upper capacitor electrode and a polysilicon layer providing sufficient resistance.
An example of a resistor pattern for use in a conventional semiconductor memory device will now be described with reference to the cross-sectional view of FIG.
1
. As shown in
FIG. 1
, an upper capacitor electrode
11
, having a relatively low resistance value, is formed on a semiconductor substrate
10
. A doped polysilicon layer
12
is formed on the other side of the upper capacitor electrode
11
. The polysilicon layer
12
can have a structure including a barrier metal of, for example, titanium nitride (TiN). As discussed above, the upper capacitor electrode
11
may be, for example, Ru or Pt. Thus, the resistor pattern in such a configuration may have the following structure: Ru/polysilicon, Pt/polysilicon, Ru/TiN/polysilcon, and/or Pt/TiN/polysilicon.
In such a conventional resistor pattern, because the doped polysilicon layer
12
is formed on an upper capacitor electrode
11
that has a relatively low resistance value (compared to the doped polysilicon layer
12
), an electrical current passing through the resistor pattern may substantially flow to the upper capacitor electrode
11
because of its relatively low resistance value. Thus, the ability to increase the resistance value of the resistor pattern based on the resistivity of the higher resistance value polysilicon layer
12
may be very limited. To avoid this problem, the doped polysilicon layer is generally not formed using the same mask as used to form the lower resistivity upper capacitor electrode
11
.
SUMMARY OF THE INVENTION
Embodiments of the present invention include methods for forming an integrated circuit device including a resistor pattern having a desired resistance value. A low resistive layer is formed on an integrated circuit substrate. An insulating layer is formed on the low resistive layer opposite the integrated circuit substrate. A high resistive layer, which may have a specific resistance of at least about a hundred &mgr;&OHgr;·cm, is formed on the insulating layer opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer define the resistor pattern in a region of the integrated circuit substrate.
In other embodiments of the present invention, the integrated circuit device is an integrated circuit memory device including a capacitor and wherein the step of forming a low resistive layer comprises concurrently forming the low resistive layer defining the resistor pattern in the region of the integrated circuit substrate and forming an upper capacitor electrode of the capacitor in a different region of the integrated circuit substrate, wherein the low resistive layer defining the resistor pattern and the upper capacitor electrode are formed of the same material.
The low resistive layer may be at least one of ruthenium (Ru), platinum (Pt), RuO
2
, Ir, IrO
2
, W, aluminum (Al), Cu, titanium nitride (TiN), tantalum nitride (TaN) and/or WN and the high resistive layer may be a doped polysilicon. The insulating layer may be at least one of SiO
2
, Ta
2
O
5
, Al
2
O
3
and/or Si
3
N
4
.
In further embodiments of the present invention, at least one of a source and/or a drain is formed in a cell region of the integrated circuit memory device between the region of the integrated circuit substrate including the resistor pattern and the different region of the integrated circuit substrate including the capacitor. A first metal contact, having a first depth, may be formed to the upper capacitor electrode and a second metal contact, having a second depth different from the first depth, may be formed to the high resistive layer of the resistor pattern. A titanium nitride (TiN) layer may be formed between the low resistive layer and the insulating layer.
In other embodiments of the present invention, methods are provided for forming an integrated circuit device including a resistor pattern having a desired resistance value. An integrated surface substrate is provided and a low resistive layer is formed defining an upper capacitor electrode in a first region of the integrated circuit substrate and a low resistive layer of the resistor pattern in a second region of the integrated circuit substrate displaced from the first region. An insulating layer is formed on the upper capacitor electrode and on the low resistive layer of the resistor pattern opposite the integrated circuit substrate. A high resistive layer is formed on the insulating layer on the upper capacitor electrode and on the low resistive layer of the resistor pattern opposite the low resistive layer. The low resistive layer, the insulating layer and the high resistive layer are formed through a single photolithography process using a common mask.
The high resistive layer may have a specific resistance of at least about a hundred &mgr;&OHgr;·cm. A metal contact may be formed to the upper capacitor electrode and a metal contact may be formed to the high resistive layer of the resistor pattern using a two photo mask process. The integrated circuit device may be an integrated circuit memory device having a junction region and the two photo mask process may further include forming a metal contact to the junction region.
In further embodiments of the present invention, the steps of forming the low resistive layer, the insulating layer and the high resistive layer may include depositing the low resistive layer over the entire surface of at least a portion of the integrated circuit substrate including the first region and the second region. The insulating layer may be deposited on the low resistive layer and the high resistive layer deposited on the insulating layer. The low resistive layer, the insulating layer and the high resistive layer may then be patterned to form the upper capacitor electrode in the first region and the resis
Park Young-Wook
Won Seok-Jun
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
LandOfFree
Integrated circuit devices including a resistor pattern and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit devices including a resistor pattern and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit devices including a resistor pattern and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3141769