Integrated circuit devices having synchronized signal...

Details Integrated circuit devices having synchronized signal... Integrated circuit devices having synchronized signal...

1999-05-25

2001-04-24

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S258000

Reexamination Certificate

active

06222411

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices which provide synchronous signal operation.
BACKGROUND OF THE INVENTION
Integrated circuit devices, such as synchronous dynamic random access memory devices (SDRAMs), utilize synchronous operation to improve device performance. For example, double data rate (DDR) SDRAMs utilize leading and trailing edges of clock signals to facilitate higher data rate operation. When SDRAMs are operated in the DDR mode, important reference signals are typically generated in-sync with rising and falling edges of a clock signal, to efficiently control operation of such devices as input and output buffers. Unfortunately, conventional attempts to detect rising and falling edges of a clock signal or other control signals may be susceptible to errors if changes in device fabrication techniques, processing conditions or signal noise are significant.
Thus, notwithstanding attempts to provide integrated circuits that operate in a synchronous manner, there continues to be a need for integrated circuits having improved synchronization characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide integrated circuit devices and signal generators that have improved synchronization characteristics.
These and other objects, advantages and features of the present invention are provided by integrated circuit devices that are capable of generating reference signals having improved synchronization characteristics. According to a preferred embodiment of the present invention, an integrated circuit device comprises a first signal generator and a second signal generator. The first signal generator receives a first input signal and a complementary version of the first input signal at true and complementary inputs thereto, respectively, and generates a first output signal having a leading edge in-sync with a leading edge of the first input signal (e.g., clock signal CLK) but delayed relative thereto by a first time interval. The second signal generator receives the first input signal and the complementary version of the first input signal at complementary and true inputs thereto, respectively, and generates a second output signal having a leading edge in-sync with a leading edge of the complementary version of the first input signal but also delayed relative thereto by the first time interval.
According to a preferred aspect of the present invention, the first and second signal generators may comprise first and second differential amplifiers, respectively. First and second pulse generators are also preferably provided. The first pulse generator is responsive to the first output signal and the second pulse generator is responsive to the second output signal. Preferably, the first pulse generator comprises a first PMOS transistor electrically connected in series between a first reference potential (e.g., Vcc) and an intermediate output node and a pair of NMOS transistors electrically connected in series between the intermediate output node and a second reference potential (e.g., Vss). The first pulse generator also preferably comprises a feedback delay circuit having an input electrically connected to the intermediate output node and an output electrically connected to a gate electrode of the first PMOS transistor. According to another preferred aspect of the first pulse generator, a first one of the pair of NMOS transistors has a gate electrode electrically connected to an output of the first signal generator and a second one of the pair of NMOS transistors has a gate electrode electrically connected to the output of the feedback delay circuit. The first pulse generator may also comprise a second PMOS transistor electrically connected in series between the first reference potential and the intermediate output node and an inverter having an input electrically connected to the intermediate output node and an output electrically connected to a gate electrode of the second PMOS transistor. The second pulse generator is constructed similarly.


REFERENCES:
patent: 5751186 (1998-05-01), Nakao
patent: 5757711 (1998-05-01), Nakaoka et al.
patent: 5764175 (1998-06-01), Pan
patent: 5801554 (1998-09-01), Momma et al.
patent: 5821809 (1998-10-01), Boerstler
patent: 5864587 (1999-01-01), Hunt
patent: 0 809 359 A1 (1997-11-01), None

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