Integrated circuit devices having data inversion circuits...

Coded data generation or conversion – Digital code to digital code converters – Substituting specified bit combinations for other prescribed...

Reexamination Certificate

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Details

C341S050000, C341S051000, C326S052000

Reexamination Certificate

active

07408482

ABSTRACT:
Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

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patent: 5477551 (1995-12-01), Parks
patent: 5881076 (1999-03-01), Murray
patent: 5915082 (1999-06-01), Marshall et al.
patent: 5931927 (1999-08-01), Takashima
patent: 6072329 (2000-06-01), Schenck
patent: 6456551 (2002-09-01), Sohn
patent: 6731567 (2004-05-01), Acharya
patent: 6735733 (2004-05-01), La Rosa
patent: 0 886 220 (1998-12-01), None
patent: WO 02/39290 (2002-05-01), None
European Search Report, European Application No. 03255882.7, Nov. 22, 2006.

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