Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-10-26
2004-07-27
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S259000, C438S296000, C438S424000, C438S433000, C438S778000
Reexamination Certificate
active
06767813
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2000-63711, filed Oct. 28, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to field effect transistors and, more particularly, to integrated circuit devices incorporating field effect transistors and methods of manufacturing same.
BACKGROUND OF THE INVENTION
As the integration density of a semiconductor chip increases, the size of a semiconductor chip generally decreases. Accordingly, as a semiconductor device, such as a dynamic random access memory (DRAM) device becomes more minute, it may be difficult to ensure that a cell transistor (cell Tr) maintains a sufficient drive capability.
In the case of a DRAM device, although the size of a memory cell transistor may decrease, the threshold voltage across a memory cell transistor is still typically kept at about 1 volt based on the refresh characteristics of the DRAM device. The gate length of a memory cell transistor and the width of an active region within a memory cell transistor may decrease as the size of a semiconductor device is reduced. To maintain the threshold voltage across a memory cell transistor at about 1 volt, channel density may be increased. Increasing the channel density, however, may cause the junction electric field to increase and the density of defects to increase, which may degrade the refresh characteristics of the DRAM device.
Also, a shallow junction is generally needed to reduce the size of a semiconductor device and to decrease the impurity concentration of a drain or a source region. Consequently, parasitic resistance may rapidly increase and the driving ability of a memory cell transistor (e.g., the current through the cell transistor) may fall sharply.
As the size of a semiconductor chip decreases and the integration density increases, shallow trench isolation (STI) may be used to isolate individual devices from each other. STI is advantageous in that it may be used as an isolation technique in devices that have high pattern densities and it generally exhibits favorable isolation characteristics. The advantages of STI notwithstanding, if a transistor has an active region with a generally small width, then the threshold voltage across the transistor may decline.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, an integrated circuit device comprises a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench. The effective width of an active region, which may act as a transistor channel under the gate electrode, may be increased by the length of the second sidewall portion of the trench. Moreover, the increased channel width of the transistor may result in an increase in the current driving capability of the transistor.
In other embodiments of the present invention, a gate insulating layer is disposed between the gate electrode and the second sidewall portion of the trench, a buffer layer is disposed between the isolation layer and the trench, and a liner layer is disposed between the isolation layer and the buffer layer.
In still other embodiments of the present invention, the second sidewall portion of the trench comprises a layer that has been doped with an impurity, such as boron.
In further embodiments of the present invention, the trench may be formed by forming an oxide layer on the substrate, forming a mask on the oxide layer, patterning the mask to expose at least a portion of the oxide layer, and then etching the exposed portion of the oxide layer.
In still further embodiments of the present invention, the isolation layer may be formed by filling the trench with insulating material so as to cover the mask. The insulating material may then be planarized until a surface of the mask is exposed. The insulating material is then patterned so that the mask extends through a surface of the insulating material. Etching is performed to substantially remove the mask from the upper surface of a mesa adjacent to the trench. The insulating material is etched so that the insulating material covers the first portion of the sidewall and exposes the second portion of the sidewall.
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Lee Kang-yoon
Park Jong-woo
Everhart Caridad
Luu Chuong Anh
Myers Bigel Sibley & Sajovec P.A.
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