Integrated circuit devices formed through selective etching...

Details Integrated circuit devices formed through selective etching... Integrated circuit devices formed through selective etching...

2005-03-22

2005-03-22

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S734000

Reexamination Certificate

active

06870268

ABSTRACT:
Integrated circuit devices and methods of manufacturing same are disclosed in which an insulation layer is selectively etched to increase the self-aligned contact area adjacent a semiconductor region. For example, a pair of interconnection patterns may be formed on a substrate with the substrate having a semiconductor region disposed between the interconnection patterns. An etch-stop layer may then be formed on the pair of interconnection patterns and the substrate followed by the formation of a sacrificial insulation on the pair of interconnection patterns and on the semiconductor region. The sacrificial insulation layer is then selectively etched to expose portions of the etch-stop layer that extend on the surfaces of the pair of interconnection patterns. Sidewall insulation spacers, which are made of a different material than the sacrificial insulation layer, may then be formed on sidewall portions of the pair of interconnection patterns in an upper gap region between the interconnection patterns and on a portion of the sacrificial insulation layer covering the semiconductor region. The portion of the sacrificial insulation layer that covers the semiconductor region may then be selectively etched, using the sidewall insulation spacers as an etching mask, to define recesses underneath the sidewall insulation spacers.

REFERENCES:
patent: 4897703 (1990-01-01), Spratt et al.
patent: 5219793 (1993-06-01), Cooper et al.
patent: 0 747 946 (1996-12-01), None
patent: WO0145156 (2001-06-01), None
Search Report, GB 0101467.9, Dec. 3, 2001, 5 pages.

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