Integrated circuit device with reduced cross talk

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S760000, C257S635000

Reexamination Certificate

active

06504250

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for producing an integrated circuit device and more particularly relates to a method for producing an integrated circuit device in which circuit cross talk is minimized by using a low dielectric constant coating material.
Cross talk between top layer metal interconnect lines of a semiconductor device can be caused by a high dielectric constant material filling the space between two metal lines. The plastic material commonly used for packaging of integrated circuits normally has a dielectric constant of between 6 and 8. As moisture penetrates the plastic material, the dielectric constant of the material increases. A higher dielectric constant increases the likelihood of capacitive coupling between adjacent metal lines.
Cross talk and capacitive effects between metal lines in a semiconductor chip are becoming greater problems with shrinking geometries and increasing chip speeds. Many of the attendant problems are difficult to model and will inexplicably show up as errors.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for minimizing circuit cross talk between adjacent metal lines in an integrated circuit device is provided. This method employs the application of a low dielectric constant material over the passivation layer of an integrated circuit semiconductor device.
It is accordingly an object of the present invention to provide a method for minimizing cross talk between adjacent metal lines in an integrated circuit device.
It is another object of the present invention to provide a method for minimizing cross talk in an integrated circuit having a passivation layer by applying a low dielectric constant material over the passivation layer.
Another object is to provide a method for minimizing cross talk in an integrated circuit which includes the steps of applying a low dielectric constant material to the integrated circuit and curing the resulting structure by heating in a suitable atmosphere.


REFERENCES:
patent: 3676756 (1972-07-01), Merrin
patent: 4039702 (1977-08-01), DiBugnara et al.
patent: 4339526 (1982-07-01), Baise et al.
patent: 4437139 (1984-03-01), Howard
patent: 4654223 (1987-03-01), Araps et al.
patent: 4656050 (1987-04-01), Araps et al.
patent: 4719125 (1988-01-01), Anello et al.
patent: 4733289 (1988-03-01), Tsurumaru
patent: 4810673 (1989-03-01), Freeman
patent: 4859253 (1989-08-01), Buchanan et al.
patent: 4965134 (1990-10-01), Ahne et al.
patent: 4965226 (1990-10-01), Gootzen et al.
patent: 5001108 (1991-03-01), Taguchi
patent: 5003062 (1991-03-01), Yen
patent: 5043789 (1991-08-01), Linde et al.
patent: 5051377 (1991-09-01), Euen et al.
patent: 5114754 (1992-05-01), Cronin et al.
patent: 5117272 (1992-05-01), Nomura et al.
patent: 5122483 (1992-06-01), Sakai et al.
patent: 5206091 (1993-04-01), Beuhler et al.
patent: 5254497 (1993-10-01), Liu
patent: 5260600 (1993-11-01), Harada
patent: 5290399 (1994-03-01), Reinhardt
patent: 5430329 (1995-07-01), Harada et al.
patent: 5438022 (1995-08-01), Allman et al.
patent: 6208029 (2001-03-01), Allman et al.
patent: 3116406 (1982-01-01), None
patent: 3805490 (1998-09-01), None
patent: 0122631 (1984-10-01), None
patent: 0501564 (1992-09-01), None
patent: 0241832 (1989-09-01), None
patent: 0030171 (1990-01-01), None
patent: 2237030 (1990-09-01), None
Silicon Processing for the VLSI Era, vol. 2: Process Integration, Stanley Wolf Ph.D., 1990, pp. 229-237.
European Patent Office publication of Patent Abstracts of Japan for Japanese Application No. 01261332, published as publication No. 03124052 on May 27, 1991.
European Patent Office publication of Patent Abstracts of Japan for Japanese Application No. 01290216, published as publication No. 03151657 on Jun. 27, 1991.
Jaouen, H., et al., “Impact of Low K Dielectric on Dynamic Electrical Performances of 0.35 &mgr;m IC,” SGS-Thomson, Crolles-France, date unknown.
Matsumoto, K., et al. “Gas Permeation of Aromatic Polyimides. I. Relationship Between Gas Permaeabilities and Dielectric Constants,” Journal of Membrane Science 81 (1993) pp 15-22 ®1993 Elsevier Science Publishers B.V.
Matsumoto, K., et al., “Gas Permeation of Aromatic Polyimides. II. Influenece of Chemical Structure,” Journal of Membrane Science 81 (1993) p 23 ®1993 Elsevier Science Publishers B.V.
Auman, Brian C., “Polymides and Copolymides with Low Dielectric Constant, Low Moisture Absorption, and Low Coefficient of Thermal Expansion for Use and Interlayer Dielectrics,” Materials Research Society Symposium Proceedings, vol. 337, ®1994 Materials Research Society, pp 705-715.

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